isa_traits.hh revision 2037
12199SN/A/* 22199SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32199SN/A * All rights reserved. 42199SN/A * 52199SN/A * Redistribution and use in source and binary forms, with or without 62199SN/A * modification, are permitted provided that the following conditions are 72199SN/A * met: redistributions of source code must retain the above copyright 82199SN/A * notice, this list of conditions and the following disclaimer; 92199SN/A * redistributions in binary form must reproduce the above copyright 102199SN/A * notice, this list of conditions and the following disclaimer in the 112199SN/A * documentation and/or other materials provided with the distribution; 122199SN/A * neither the name of the copyright holders nor the names of its 132199SN/A * contributors may be used to endorse or promote products derived from 142199SN/A * this software without specific prior written permission. 152199SN/A * 162199SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172199SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182199SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192199SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202199SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212199SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222199SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232199SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242199SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252199SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262199SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu */ 282665Ssaidi@eecs.umich.edu 292665Ssaidi@eecs.umich.edu#ifndef __ARCH_ALPHA_ISA_TRAITS_HH__ 302665Ssaidi@eecs.umich.edu#define __ARCH_ALPHA_ISA_TRAITS_HH__ 312199SN/A 322199SN/Anamespace LittleEndianGuest {} 332561SN/Ausing namespace LittleEndianGuest; 342226SN/A 352561SN/A#include "arch/alpha/faults.hh" 362199SN/A#include "base/misc.hh" 372199SN/A#include "config/full_system.hh" 382680Sktlim@umich.edu#include "sim/host.hh" 392199SN/A 402199SN/Aclass FastCPU; 412199SN/Aclass FullCPU; 422199SN/Aclass Checkpoint; 432199SN/A 442199SN/A#define TARGET_ALPHA 452209SN/A 462199SN/Atemplate <class ISA> class StaticInst; 472199SN/Atemplate <class ISA> class StaticInstPtr; 482458SN/A 492199SN/Anamespace EV5 { 502199SN/Aint DTB_ASN_ASN(uint64_t reg); 512199SN/Aint ITB_ASN_ASN(uint64_t reg); 522199SN/A} 532199SN/A 544111Sgblack@eecs.umich.educlass AlphaISA 554188Sgblack@eecs.umich.edu{ 564188Sgblack@eecs.umich.edu public: 574188Sgblack@eecs.umich.edu 584188Sgblack@eecs.umich.edu typedef uint32_t MachInst; 594188Sgblack@eecs.umich.edu typedef uint64_t Addr; 604188Sgblack@eecs.umich.edu typedef uint8_t RegIndex; 614188Sgblack@eecs.umich.edu 624111Sgblack@eecs.umich.edu enum { 634111Sgblack@eecs.umich.edu MemoryEnd = 0xffffffffffffffffULL, 644188Sgblack@eecs.umich.edu 654188Sgblack@eecs.umich.edu NumIntRegs = 32, 664111Sgblack@eecs.umich.edu NumFloatRegs = 32, 674111Sgblack@eecs.umich.edu NumMiscRegs = 32, 684111Sgblack@eecs.umich.edu 694111Sgblack@eecs.umich.edu MaxRegsOfAnyType = 32, 704188Sgblack@eecs.umich.edu // Static instruction parameters 714188Sgblack@eecs.umich.edu MaxInstSrcRegs = 3, 724188Sgblack@eecs.umich.edu MaxInstDestRegs = 2, 734111Sgblack@eecs.umich.edu 744111Sgblack@eecs.umich.edu // semantically meaningful register indices 755154Sgblack@eecs.umich.edu ZeroReg = 31, // architecturally meaningful 765154Sgblack@eecs.umich.edu // the rest of these depend on the ABI 775154Sgblack@eecs.umich.edu StackPointerReg = 30, 784111Sgblack@eecs.umich.edu GlobalPointerReg = 29, 794111Sgblack@eecs.umich.edu ProcedureValueReg = 27, 804111Sgblack@eecs.umich.edu ReturnAddressReg = 26, 814111Sgblack@eecs.umich.edu ReturnValueReg = 0, 824111Sgblack@eecs.umich.edu FramePointerReg = 15, 834111Sgblack@eecs.umich.edu ArgumentReg0 = 16, 844111Sgblack@eecs.umich.edu ArgumentReg1 = 17, 854111Sgblack@eecs.umich.edu ArgumentReg2 = 18, 864111Sgblack@eecs.umich.edu ArgumentReg3 = 19, 874111Sgblack@eecs.umich.edu ArgumentReg4 = 20, 884111Sgblack@eecs.umich.edu ArgumentReg5 = 21, 894111Sgblack@eecs.umich.edu 904111Sgblack@eecs.umich.edu LogVMPageSize = 13, // 8K bytes 914111Sgblack@eecs.umich.edu VMPageSize = (1 << LogVMPageSize), 925154Sgblack@eecs.umich.edu 935154Sgblack@eecs.umich.edu BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned 945154Sgblack@eecs.umich.edu 954111Sgblack@eecs.umich.edu WordBytes = 4, 964111Sgblack@eecs.umich.edu HalfwordBytes = 2, 974111Sgblack@eecs.umich.edu ByteBytes = 1, 984111Sgblack@eecs.umich.edu DepNA = 0, 994111Sgblack@eecs.umich.edu }; 1004111Sgblack@eecs.umich.edu 1014188Sgblack@eecs.umich.edu // These enumerate all the registers for dependence tracking. 1024111Sgblack@eecs.umich.edu enum DependenceTags { 1034111Sgblack@eecs.umich.edu // 0..31 are the integer regs 0..31 1044111Sgblack@eecs.umich.edu // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag) 1054111Sgblack@eecs.umich.edu FP_Base_DepTag = 32, 1064111Sgblack@eecs.umich.edu Ctrl_Base_DepTag = 64, 1074111Sgblack@eecs.umich.edu Fpcr_DepTag = 64, // floating point control register 1084111Sgblack@eecs.umich.edu Uniq_DepTag = 65, 109 IPR_Base_DepTag = 66 110 }; 111 112 typedef uint64_t IntReg; 113 typedef IntReg IntRegFile[NumIntRegs]; 114 115 // floating point register file entry type 116 typedef union { 117 uint64_t q; 118 double d; 119 } FloatReg; 120 121 typedef union { 122 uint64_t q[NumFloatRegs]; // integer qword view 123 double d[NumFloatRegs]; // double-precision floating point view 124 } FloatRegFile; 125 126 // control register file contents 127 typedef uint64_t MiscReg; 128 typedef struct { 129 uint64_t fpcr; // floating point condition codes 130 uint64_t uniq; // process-unique register 131 bool lock_flag; // lock flag for LL/SC 132 Addr lock_addr; // lock address for LL/SC 133 } MiscRegFile; 134 135static const Addr PageShift = 13; 136static const Addr PageBytes = ULL(1) << PageShift; 137static const Addr PageMask = ~(PageBytes - 1); 138static const Addr PageOffset = PageBytes - 1; 139 140#if FULL_SYSTEM 141 142 typedef uint64_t InternalProcReg; 143 144#include "arch/alpha/isa_fullsys_traits.hh" 145 146#else 147 enum { 148 NumInternalProcRegs = 0 149 }; 150#endif 151 152 enum { 153 TotalNumRegs = 154 NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs 155 }; 156 157 enum { 158 TotalDataRegs = NumIntRegs + NumFloatRegs 159 }; 160 161 typedef union { 162 IntReg intreg; 163 FloatReg fpreg; 164 MiscReg ctrlreg; 165 } AnyReg; 166 167 struct RegFile { 168 IntRegFile intRegFile; // (signed) integer register file 169 FloatRegFile floatRegFile; // floating point register file 170 MiscRegFile miscRegs; // control register file 171 Addr pc; // program counter 172 Addr npc; // next-cycle program counter 173#if FULL_SYSTEM 174 IntReg palregs[NumIntRegs]; // PAL shadow registers 175 InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs 176 int intrflag; // interrupt flag 177 bool pal_shadow; // using pal_shadow registers 178 inline int instAsid() { return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); } 179 inline int dataAsid() { return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); } 180#endif // FULL_SYSTEM 181 182 void serialize(std::ostream &os); 183 void unserialize(Checkpoint *cp, const std::string §ion); 184 }; 185 186 static StaticInstPtr<AlphaISA> decodeInst(MachInst); 187 188 // return a no-op instruction... used for instruction fetch faults 189 static const MachInst NoopMachInst; 190 191 enum annotes { 192 ANNOTE_NONE = 0, 193 // An impossible number for instruction annotations 194 ITOUCH_ANNOTE = 0xffffffff, 195 }; 196 197 static inline bool isCallerSaveIntegerRegister(unsigned int reg) { 198 panic("register classification not implemented"); 199 return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27); 200 } 201 202 static inline bool isCalleeSaveIntegerRegister(unsigned int reg) { 203 panic("register classification not implemented"); 204 return (reg >= 9 && reg <= 15); 205 } 206 207 static inline bool isCallerSaveFloatRegister(unsigned int reg) { 208 panic("register classification not implemented"); 209 return false; 210 } 211 212 static inline bool isCalleeSaveFloatRegister(unsigned int reg) { 213 panic("register classification not implemented"); 214 return false; 215 } 216 217 static inline Addr alignAddress(const Addr &addr, 218 unsigned int nbytes) { 219 return (addr & ~(nbytes - 1)); 220 } 221 222 // Instruction address compression hooks 223 static inline Addr realPCToFetchPC(const Addr &addr) { 224 return addr; 225 } 226 227 static inline Addr fetchPCToRealPC(const Addr &addr) { 228 return addr; 229 } 230 231 // the size of "fetched" instructions (not necessarily the size 232 // of real instructions for PISA) 233 static inline size_t fetchInstSize() { 234 return sizeof(MachInst); 235 } 236 237 static inline MachInst makeRegisterCopy(int dest, int src) { 238 panic("makeRegisterCopy not implemented"); 239 return 0; 240 } 241 242 // Machine operations 243 244 static void saveMachineReg(AnyReg &savereg, const RegFile ®_file, 245 int regnum); 246 247 static void restoreMachineReg(RegFile ®s, const AnyReg ®, 248 int regnum); 249 250#if 0 251 static void serializeSpecialRegs(const Serializable::Proxy &proxy, 252 const RegFile ®s); 253 254 static void unserializeSpecialRegs(const IniFile *db, 255 const std::string &category, 256 ConfigNode *node, 257 RegFile ®s); 258#endif 259 260 /** 261 * Function to insure ISA semantics about 0 registers. 262 * @param xc The execution context. 263 */ 264 template <class XC> 265 static void zeroRegisters(XC *xc); 266}; 267 268 269typedef AlphaISA TheISA; 270 271typedef TheISA::MachInst MachInst; 272typedef TheISA::Addr Addr; 273typedef TheISA::RegIndex RegIndex; 274typedef TheISA::IntReg IntReg; 275typedef TheISA::IntRegFile IntRegFile; 276typedef TheISA::FloatReg FloatReg; 277typedef TheISA::FloatRegFile FloatRegFile; 278typedef TheISA::MiscReg MiscReg; 279typedef TheISA::MiscRegFile MiscRegFile; 280typedef TheISA::AnyReg AnyReg; 281typedef TheISA::RegFile RegFile; 282 283const int NumIntRegs = TheISA::NumIntRegs; 284const int NumFloatRegs = TheISA::NumFloatRegs; 285const int NumMiscRegs = TheISA::NumMiscRegs; 286const int TotalNumRegs = TheISA::TotalNumRegs; 287const int VMPageSize = TheISA::VMPageSize; 288const int LogVMPageSize = TheISA::LogVMPageSize; 289const int ZeroReg = TheISA::ZeroReg; 290const int StackPointerReg = TheISA::StackPointerReg; 291const int GlobalPointerReg = TheISA::GlobalPointerReg; 292const int ReturnAddressReg = TheISA::ReturnAddressReg; 293const int ReturnValueReg = TheISA::ReturnValueReg; 294const int ArgumentReg0 = TheISA::ArgumentReg0; 295const int ArgumentReg1 = TheISA::ArgumentReg1; 296const int ArgumentReg2 = TheISA::ArgumentReg2; 297const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt; 298const int MaxAddr = (Addr)-1; 299 300#if !FULL_SYSTEM 301class SyscallReturn { 302 public: 303 template <class T> 304 SyscallReturn(T v, bool s) 305 { 306 retval = (uint64_t)v; 307 success = s; 308 } 309 310 template <class T> 311 SyscallReturn(T v) 312 { 313 success = (v >= 0); 314 retval = (uint64_t)v; 315 } 316 317 ~SyscallReturn() {} 318 319 SyscallReturn& operator=(const SyscallReturn& s) { 320 retval = s.retval; 321 success = s.success; 322 return *this; 323 } 324 325 bool successful() { return success; } 326 uint64_t value() { return retval; } 327 328 329 private: 330 uint64_t retval; 331 bool success; 332}; 333 334#endif 335 336 337#if FULL_SYSTEM 338typedef TheISA::InternalProcReg InternalProcReg; 339const int NumInternalProcRegs = TheISA::NumInternalProcRegs; 340const int NumInterruptLevels = TheISA::NumInterruptLevels; 341 342#include "arch/alpha/ev5.hh" 343#endif 344 345#endif // __ARCH_ALPHA_ISA_TRAITS_HH__ 346