isa_traits.hh revision 2037 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __ARCH_ALPHA_ISA_TRAITS_HH__
30#define __ARCH_ALPHA_ISA_TRAITS_HH__
31
32namespace LittleEndianGuest {}
33using namespace LittleEndianGuest;
34
35#include "arch/alpha/faults.hh"
36#include "base/misc.hh"
37#include "config/full_system.hh"
38#include "sim/host.hh"
39
40class FastCPU;
41class FullCPU;
42class Checkpoint;
43
44#define TARGET_ALPHA
45
46template <class ISA> class StaticInst;
47template <class ISA> class StaticInstPtr;
48
49namespace EV5 {
50int DTB_ASN_ASN(uint64_t reg);
51int ITB_ASN_ASN(uint64_t reg);
52}
53
54class AlphaISA
55{
56  public:
57
58    typedef uint32_t MachInst;
59    typedef uint64_t Addr;
60    typedef uint8_t  RegIndex;
61
62    enum {
63        MemoryEnd = 0xffffffffffffffffULL,
64
65        NumIntRegs = 32,
66        NumFloatRegs = 32,
67        NumMiscRegs = 32,
68
69        MaxRegsOfAnyType = 32,
70        // Static instruction parameters
71        MaxInstSrcRegs = 3,
72        MaxInstDestRegs = 2,
73
74        // semantically meaningful register indices
75        ZeroReg = 31,	// architecturally meaningful
76        // the rest of these depend on the ABI
77        StackPointerReg = 30,
78        GlobalPointerReg = 29,
79        ProcedureValueReg = 27,
80        ReturnAddressReg = 26,
81        ReturnValueReg = 0,
82        FramePointerReg = 15,
83        ArgumentReg0 = 16,
84        ArgumentReg1 = 17,
85        ArgumentReg2 = 18,
86        ArgumentReg3 = 19,
87        ArgumentReg4 = 20,
88        ArgumentReg5 = 21,
89
90        LogVMPageSize = 13,	// 8K bytes
91        VMPageSize = (1 << LogVMPageSize),
92
93        BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned
94
95        WordBytes = 4,
96        HalfwordBytes = 2,
97        ByteBytes = 1,
98        DepNA = 0,
99    };
100
101    // These enumerate all the registers for dependence tracking.
102    enum DependenceTags {
103        // 0..31 are the integer regs 0..31
104        // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
105        FP_Base_DepTag = 32,
106        Ctrl_Base_DepTag = 64,
107        Fpcr_DepTag = 64,		// floating point control register
108        Uniq_DepTag = 65,
109        IPR_Base_DepTag = 66
110    };
111
112    typedef uint64_t IntReg;
113    typedef IntReg IntRegFile[NumIntRegs];
114
115    // floating point register file entry type
116    typedef union {
117        uint64_t q;
118        double d;
119    } FloatReg;
120
121    typedef union {
122        uint64_t q[NumFloatRegs];	// integer qword view
123        double d[NumFloatRegs];		// double-precision floating point view
124    } FloatRegFile;
125
126    // control register file contents
127    typedef uint64_t MiscReg;
128    typedef struct {
129        uint64_t	fpcr;		// floating point condition codes
130        uint64_t	uniq;		// process-unique register
131        bool		lock_flag;	// lock flag for LL/SC
132        Addr		lock_addr;	// lock address for LL/SC
133    } MiscRegFile;
134
135static const Addr PageShift = 13;
136static const Addr PageBytes = ULL(1) << PageShift;
137static const Addr PageMask = ~(PageBytes - 1);
138static const Addr PageOffset = PageBytes - 1;
139
140#if FULL_SYSTEM
141
142    typedef uint64_t InternalProcReg;
143
144#include "arch/alpha/isa_fullsys_traits.hh"
145
146#else
147    enum {
148        NumInternalProcRegs = 0
149    };
150#endif
151
152    enum {
153        TotalNumRegs =
154        NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs
155    };
156
157    enum {
158        TotalDataRegs = NumIntRegs + NumFloatRegs
159    };
160
161    typedef union {
162        IntReg  intreg;
163        FloatReg   fpreg;
164        MiscReg ctrlreg;
165    } AnyReg;
166
167    struct RegFile {
168        IntRegFile intRegFile;		// (signed) integer register file
169        FloatRegFile floatRegFile;	// floating point register file
170        MiscRegFile miscRegs;		// control register file
171        Addr pc;			// program counter
172        Addr npc;			// next-cycle program counter
173#if FULL_SYSTEM
174        IntReg palregs[NumIntRegs];	// PAL shadow registers
175        InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs
176        int intrflag;			// interrupt flag
177        bool pal_shadow;		// using pal_shadow registers
178        inline int instAsid() { return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); }
179        inline int dataAsid() { return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); }
180#endif // FULL_SYSTEM
181
182        void serialize(std::ostream &os);
183        void unserialize(Checkpoint *cp, const std::string &section);
184    };
185
186    static StaticInstPtr<AlphaISA> decodeInst(MachInst);
187
188    // return a no-op instruction... used for instruction fetch faults
189    static const MachInst NoopMachInst;
190
191    enum annotes {
192        ANNOTE_NONE = 0,
193        // An impossible number for instruction annotations
194        ITOUCH_ANNOTE = 0xffffffff,
195    };
196
197    static inline bool isCallerSaveIntegerRegister(unsigned int reg) {
198        panic("register classification not implemented");
199        return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
200    }
201
202    static inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
203        panic("register classification not implemented");
204        return (reg >= 9 && reg <= 15);
205    }
206
207    static inline bool isCallerSaveFloatRegister(unsigned int reg) {
208        panic("register classification not implemented");
209        return false;
210    }
211
212    static inline bool isCalleeSaveFloatRegister(unsigned int reg) {
213        panic("register classification not implemented");
214        return false;
215    }
216
217    static inline Addr alignAddress(const Addr &addr,
218                                         unsigned int nbytes) {
219        return (addr & ~(nbytes - 1));
220    }
221
222    // Instruction address compression hooks
223    static inline Addr realPCToFetchPC(const Addr &addr) {
224        return addr;
225    }
226
227    static inline Addr fetchPCToRealPC(const Addr &addr) {
228        return addr;
229    }
230
231    // the size of "fetched" instructions (not necessarily the size
232    // of real instructions for PISA)
233    static inline size_t fetchInstSize() {
234        return sizeof(MachInst);
235    }
236
237    static inline MachInst makeRegisterCopy(int dest, int src) {
238        panic("makeRegisterCopy not implemented");
239        return 0;
240    }
241
242    // Machine operations
243
244    static void saveMachineReg(AnyReg &savereg, const RegFile &reg_file,
245                               int regnum);
246
247    static void restoreMachineReg(RegFile &regs, const AnyReg &reg,
248                                  int regnum);
249
250#if 0
251    static void serializeSpecialRegs(const Serializable::Proxy &proxy,
252                                     const RegFile &regs);
253
254    static void unserializeSpecialRegs(const IniFile *db,
255                                       const std::string &category,
256                                       ConfigNode *node,
257                                       RegFile &regs);
258#endif
259
260    /**
261     * Function to insure ISA semantics about 0 registers.
262     * @param xc The execution context.
263     */
264    template <class XC>
265    static void zeroRegisters(XC *xc);
266};
267
268
269typedef AlphaISA TheISA;
270
271typedef TheISA::MachInst MachInst;
272typedef TheISA::Addr Addr;
273typedef TheISA::RegIndex RegIndex;
274typedef TheISA::IntReg IntReg;
275typedef TheISA::IntRegFile IntRegFile;
276typedef TheISA::FloatReg FloatReg;
277typedef TheISA::FloatRegFile FloatRegFile;
278typedef TheISA::MiscReg MiscReg;
279typedef TheISA::MiscRegFile MiscRegFile;
280typedef TheISA::AnyReg AnyReg;
281typedef TheISA::RegFile RegFile;
282
283const int NumIntRegs   = TheISA::NumIntRegs;
284const int NumFloatRegs = TheISA::NumFloatRegs;
285const int NumMiscRegs  = TheISA::NumMiscRegs;
286const int TotalNumRegs = TheISA::TotalNumRegs;
287const int VMPageSize   = TheISA::VMPageSize;
288const int LogVMPageSize   = TheISA::LogVMPageSize;
289const int ZeroReg = TheISA::ZeroReg;
290const int StackPointerReg = TheISA::StackPointerReg;
291const int GlobalPointerReg = TheISA::GlobalPointerReg;
292const int ReturnAddressReg = TheISA::ReturnAddressReg;
293const int ReturnValueReg = TheISA::ReturnValueReg;
294const int ArgumentReg0 = TheISA::ArgumentReg0;
295const int ArgumentReg1 = TheISA::ArgumentReg1;
296const int ArgumentReg2 = TheISA::ArgumentReg2;
297const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt;
298const int MaxAddr = (Addr)-1;
299
300#if !FULL_SYSTEM
301class SyscallReturn {
302        public:
303           template <class T>
304           SyscallReturn(T v, bool s)
305           {
306               retval = (uint64_t)v;
307               success = s;
308           }
309
310           template <class T>
311           SyscallReturn(T v)
312           {
313               success = (v >= 0);
314               retval = (uint64_t)v;
315           }
316
317           ~SyscallReturn() {}
318
319           SyscallReturn& operator=(const SyscallReturn& s) {
320               retval = s.retval;
321               success = s.success;
322               return *this;
323           }
324
325           bool successful() { return success; }
326           uint64_t value() { return retval; }
327
328
329       private:
330           uint64_t retval;
331           bool success;
332};
333
334#endif
335
336
337#if FULL_SYSTEM
338typedef TheISA::InternalProcReg InternalProcReg;
339const int NumInternalProcRegs  = TheISA::NumInternalProcRegs;
340const int NumInterruptLevels = TheISA::NumInterruptLevels;
341
342#include "arch/alpha/ev5.hh"
343#endif
344
345#endif // __ARCH_ALPHA_ISA_TRAITS_HH__
346