decoder.isa revision 2284
1955SN/A// -*- mode:c++ -*- 2955SN/A 31762SN/A// Copyright (c) 2003-2006 The Regents of The University of Michigan 4955SN/A// All rights reserved. 5955SN/A// 6955SN/A// Redistribution and use in source and binary forms, with or without 7955SN/A// modification, are permitted provided that the following conditions are 8955SN/A// met: redistributions of source code must retain the above copyright 9955SN/A// notice, this list of conditions and the following disclaimer; 10955SN/A// redistributions in binary form must reproduce the above copyright 11955SN/A// notice, this list of conditions and the following disclaimer in the 12955SN/A// documentation and/or other materials provided with the distribution; 13955SN/A// neither the name of the copyright holders nor the names of its 14955SN/A// contributors may be used to endorse or promote products derived from 15955SN/A// this software without specific prior written permission. 16955SN/A// 17955SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18955SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19955SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20955SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21955SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22955SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23955SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24955SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25955SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26955SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27955SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu 294762Snate@binkert.orgdecode OPCODE default Unknown::unknown() { 30955SN/A 3112563Sgabeblack@google.com format LoadAddress { 3212563Sgabeblack@google.com 0x08: lda({{ Ra = Rb + disp; }}); 335522Snate@binkert.org 0x09: ldah({{ Ra = Rb + (disp << 16); }}); 346143Snate@binkert.org } 3512371Sgabeblack@google.com 364762Snate@binkert.org format LoadOrNop { 375522Snate@binkert.org 0x0a: ldbu({{ Ra.uq = Mem.ub; }}); 38955SN/A 0x0c: ldwu({{ Ra.uq = Mem.uw; }}); 395522Snate@binkert.org 0x0b: ldq_u({{ Ra = Mem.uq; }}, ea_code = {{ EA = (Rb + disp) & ~7; }}); 4011974Sgabeblack@google.com 0x23: ldt({{ Fa = Mem.df; }}); 41955SN/A 0x2a: ldl_l({{ Ra.sl = Mem.sl; }}, mem_flags = LOCKED); 425522Snate@binkert.org 0x2b: ldq_l({{ Ra.uq = Mem.uq; }}, mem_flags = LOCKED); 434202Sbinkertn@umich.edu 0x20: MiscPrefetch::copy_load({{ EA = Ra; }}, 445742Snate@binkert.org {{ fault = xc->copySrcTranslate(EA); }}, 45955SN/A inst_flags = [IsMemRef, IsLoad, IsCopy]); 464381Sbinkertn@umich.edu } 474381Sbinkertn@umich.edu 4812246Sgabeblack@google.com format LoadOrPrefetch { 4912246Sgabeblack@google.com 0x28: ldl({{ Ra.sl = Mem.sl; }}); 508334Snate@binkert.org 0x29: ldq({{ Ra.uq = Mem.uq; }}, pf_flags = EVICT_NEXT); 51955SN/A // IsFloating flag on lds gets the prefetch to disassemble 52955SN/A // using f31 instead of r31... funcitonally it's unnecessary 534202Sbinkertn@umich.edu 0x22: lds({{ Fa.uq = s_to_t(Mem.ul); }}, 54955SN/A pf_flags = PF_EXCLUSIVE, inst_flags = IsFloating); 554382Sbinkertn@umich.edu } 564382Sbinkertn@umich.edu 574382Sbinkertn@umich.edu format Store { 586654Snate@binkert.org 0x0e: stb({{ Mem.ub = Ra<7:0>; }}); 595517Snate@binkert.org 0x0d: stw({{ Mem.uw = Ra<15:0>; }}); 608614Sgblack@eecs.umich.edu 0x2c: stl({{ Mem.ul = Ra<31:0>; }}); 617674Snate@binkert.org 0x2d: stq({{ Mem.uq = Ra.uq; }}); 626143Snate@binkert.org 0x0f: stq_u({{ Mem.uq = Ra.uq; }}, {{ EA = (Rb + disp) & ~7; }}); 636143Snate@binkert.org 0x26: sts({{ Mem.ul = t_to_s(Fa.uq); }}); 646143Snate@binkert.org 0x27: stt({{ Mem.df = Fa; }}); 6512302Sgabeblack@google.com 0x24: MiscPrefetch::copy_store({{ EA = Rb; }}, 6612302Sgabeblack@google.com {{ fault = xc->copy(EA); }}, 6712302Sgabeblack@google.com inst_flags = [IsMemRef, IsStore, IsCopy]); 6812371Sgabeblack@google.com } 6912371Sgabeblack@google.com 7012371Sgabeblack@google.com format StoreCond { 7112371Sgabeblack@google.com 0x2e: stl_c({{ Mem.ul = Ra<31:0>; }}, 7212371Sgabeblack@google.com {{ 7312371Sgabeblack@google.com uint64_t tmp = write_result; 7412371Sgabeblack@google.com // see stq_c 7512371Sgabeblack@google.com Ra = (tmp == 0 || tmp == 1) ? tmp : Ra; 7612371Sgabeblack@google.com }}, mem_flags = LOCKED); 7712371Sgabeblack@google.com 0x2f: stq_c({{ Mem.uq = Ra; }}, 7812371Sgabeblack@google.com {{ 7912371Sgabeblack@google.com uint64_t tmp = write_result; 8012371Sgabeblack@google.com // If the write operation returns 0 or 1, then 8112371Sgabeblack@google.com // this was a conventional store conditional, 8212371Sgabeblack@google.com // and the value indicates the success/failure 8312371Sgabeblack@google.com // of the operation. If another value is 8412371Sgabeblack@google.com // returned, then this was a Turbolaser 8512371Sgabeblack@google.com // mailbox access, and we don't update the 8612371Sgabeblack@google.com // result register at all. 8712371Sgabeblack@google.com Ra = (tmp == 0 || tmp == 1) ? tmp : Ra; 8812371Sgabeblack@google.com }}, mem_flags = LOCKED); 8912371Sgabeblack@google.com } 9012371Sgabeblack@google.com 9112371Sgabeblack@google.com format IntegerOperate { 9212371Sgabeblack@google.com 9312371Sgabeblack@google.com 0x10: decode INTFUNC { // integer arithmetic operations 9412371Sgabeblack@google.com 9512371Sgabeblack@google.com 0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }}); 9612371Sgabeblack@google.com 0x40: addlv({{ 9712371Sgabeblack@google.com uint32_t tmp = Ra.sl + Rb_or_imm.sl; 9812371Sgabeblack@google.com // signed overflow occurs when operands have same sign 9912371Sgabeblack@google.com // and sign of result does not match. 10012371Sgabeblack@google.com if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>) 10112371Sgabeblack@google.com fault = new IntegerOverflowFault; 10212371Sgabeblack@google.com Rc.sl = tmp; 10312371Sgabeblack@google.com }}); 10412371Sgabeblack@google.com 0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }}); 10512371Sgabeblack@google.com 0x12: s8addl({{ Rc.sl = (Ra.sl << 3) + Rb_or_imm.sl; }}); 10612371Sgabeblack@google.com 10712371Sgabeblack@google.com 0x20: addq({{ Rc = Ra + Rb_or_imm; }}); 10812371Sgabeblack@google.com 0x60: addqv({{ 10912371Sgabeblack@google.com uint64_t tmp = Ra + Rb_or_imm; 11012371Sgabeblack@google.com // signed overflow occurs when operands have same sign 11112371Sgabeblack@google.com // and sign of result does not match. 11212371Sgabeblack@google.com if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>) 11312371Sgabeblack@google.com fault = new IntegerOverflowFault; 11412371Sgabeblack@google.com Rc = tmp; 11512302Sgabeblack@google.com }}); 11612371Sgabeblack@google.com 0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }}); 11712302Sgabeblack@google.com 0x32: s8addq({{ Rc = (Ra << 3) + Rb_or_imm; }}); 11812371Sgabeblack@google.com 11912302Sgabeblack@google.com 0x09: subl({{ Rc.sl = Ra.sl - Rb_or_imm.sl; }}); 12012302Sgabeblack@google.com 0x49: sublv({{ 12112371Sgabeblack@google.com uint32_t tmp = Ra.sl - Rb_or_imm.sl; 12212371Sgabeblack@google.com // signed overflow detection is same as for add, 12312371Sgabeblack@google.com // except we need to look at the *complemented* 12412371Sgabeblack@google.com // sign bit of the subtrahend (Rb), i.e., if the initial 12512302Sgabeblack@google.com // signs are the *same* then no overflow can occur 12612371Sgabeblack@google.com if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>) 12712371Sgabeblack@google.com fault = new IntegerOverflowFault; 12812371Sgabeblack@google.com Rc.sl = tmp; 12912371Sgabeblack@google.com }}); 13011983Sgabeblack@google.com 0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }}); 1316143Snate@binkert.org 0x1b: s8subl({{ Rc.sl = (Ra.sl << 3) - Rb_or_imm.sl; }}); 1328233Snate@binkert.org 13312302Sgabeblack@google.com 0x29: subq({{ Rc = Ra - Rb_or_imm; }}); 1346143Snate@binkert.org 0x69: subqv({{ 1356143Snate@binkert.org uint64_t tmp = Ra - Rb_or_imm; 13612302Sgabeblack@google.com // signed overflow detection is same as for add, 1374762Snate@binkert.org // except we need to look at the *complemented* 1386143Snate@binkert.org // sign bit of the subtrahend (Rb), i.e., if the initial 1398233Snate@binkert.org // signs are the *same* then no overflow can occur 1408233Snate@binkert.org if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>) 14112302Sgabeblack@google.com fault = new IntegerOverflowFault; 14212302Sgabeblack@google.com Rc = tmp; 1436143Snate@binkert.org }}); 14412362Sgabeblack@google.com 0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }}); 14512362Sgabeblack@google.com 0x3b: s8subq({{ Rc = (Ra << 3) - Rb_or_imm; }}); 14612362Sgabeblack@google.com 14712362Sgabeblack@google.com 0x2d: cmpeq({{ Rc = (Ra == Rb_or_imm); }}); 14812302Sgabeblack@google.com 0x6d: cmple({{ Rc = (Ra.sq <= Rb_or_imm.sq); }}); 14912302Sgabeblack@google.com 0x4d: cmplt({{ Rc = (Ra.sq < Rb_or_imm.sq); }}); 15012302Sgabeblack@google.com 0x3d: cmpule({{ Rc = (Ra.uq <= Rb_or_imm.uq); }}); 15112302Sgabeblack@google.com 0x1d: cmpult({{ Rc = (Ra.uq < Rb_or_imm.uq); }}); 15212302Sgabeblack@google.com 15312363Sgabeblack@google.com 0x0f: cmpbge({{ 15412363Sgabeblack@google.com int hi = 7; 15512363Sgabeblack@google.com int lo = 0; 15612363Sgabeblack@google.com uint64_t tmp = 0; 15712302Sgabeblack@google.com for (int i = 0; i < 8; ++i) { 15812363Sgabeblack@google.com tmp |= (Ra.uq<hi:lo> >= Rb_or_imm.uq<hi:lo>) << i; 15912363Sgabeblack@google.com hi += 8; 16012363Sgabeblack@google.com lo += 8; 16112363Sgabeblack@google.com } 16212363Sgabeblack@google.com Rc = tmp; 1638233Snate@binkert.org }}); 1646143Snate@binkert.org } 1656143Snate@binkert.org 1666143Snate@binkert.org 0x11: decode INTFUNC { // integer logical operations 1676143Snate@binkert.org 1686143Snate@binkert.org 0x00: and({{ Rc = Ra & Rb_or_imm; }}); 1696143Snate@binkert.org 0x08: bic({{ Rc = Ra & ~Rb_or_imm; }}); 1706143Snate@binkert.org 0x20: bis({{ Rc = Ra | Rb_or_imm; }}); 1716143Snate@binkert.org 0x28: ornot({{ Rc = Ra | ~Rb_or_imm; }}); 1726143Snate@binkert.org 0x40: xor({{ Rc = Ra ^ Rb_or_imm; }}); 1737065Snate@binkert.org 0x48: eqv({{ Rc = Ra ^ ~Rb_or_imm; }}); 1746143Snate@binkert.org 17512362Sgabeblack@google.com // conditional moves 17612362Sgabeblack@google.com 0x14: cmovlbs({{ Rc = ((Ra & 1) == 1) ? Rb_or_imm : Rc; }}); 17712362Sgabeblack@google.com 0x16: cmovlbc({{ Rc = ((Ra & 1) == 0) ? Rb_or_imm : Rc; }}); 17812362Sgabeblack@google.com 0x24: cmoveq({{ Rc = (Ra == 0) ? Rb_or_imm : Rc; }}); 17912362Sgabeblack@google.com 0x26: cmovne({{ Rc = (Ra != 0) ? Rb_or_imm : Rc; }}); 18012362Sgabeblack@google.com 0x44: cmovlt({{ Rc = (Ra.sq < 0) ? Rb_or_imm : Rc; }}); 18112362Sgabeblack@google.com 0x46: cmovge({{ Rc = (Ra.sq >= 0) ? Rb_or_imm : Rc; }}); 18212362Sgabeblack@google.com 0x64: cmovle({{ Rc = (Ra.sq <= 0) ? Rb_or_imm : Rc; }}); 18312362Sgabeblack@google.com 0x66: cmovgt({{ Rc = (Ra.sq > 0) ? Rb_or_imm : Rc; }}); 18412362Sgabeblack@google.com 18512362Sgabeblack@google.com // For AMASK, RA must be R31. 18612362Sgabeblack@google.com 0x61: decode RA { 1878233Snate@binkert.org 31: amask({{ Rc = Rb_or_imm & ~ULL(0x17); }}); 1888233Snate@binkert.org } 1898233Snate@binkert.org 1908233Snate@binkert.org // For IMPLVER, RA must be R31 and the B operand 1918233Snate@binkert.org // must be the immediate value 1. 1928233Snate@binkert.org 0x6c: decode RA { 1938233Snate@binkert.org 31: decode IMM { 1948233Snate@binkert.org 1: decode INTIMM { 1958233Snate@binkert.org // return EV5 for FULL_SYSTEM and EV6 otherwise 1968233Snate@binkert.org 1: implver({{ 1978233Snate@binkert.org#if FULL_SYSTEM 1988233Snate@binkert.org Rc = 1; 1998233Snate@binkert.org#else 2008233Snate@binkert.org Rc = 2; 2018233Snate@binkert.org#endif 2028233Snate@binkert.org }}); 2038233Snate@binkert.org } 2048233Snate@binkert.org } 2058233Snate@binkert.org } 2068233Snate@binkert.org 2078233Snate@binkert.org#if FULL_SYSTEM 2086143Snate@binkert.org // The mysterious 11.25... 2096143Snate@binkert.org 0x25: WarnUnimpl::eleven25(); 2106143Snate@binkert.org#endif 2116143Snate@binkert.org } 2126143Snate@binkert.org 2136143Snate@binkert.org 0x12: decode INTFUNC { 2149982Satgutier@umich.edu 0x39: sll({{ Rc = Ra << Rb_or_imm<5:0>; }}); 2156143Snate@binkert.org 0x34: srl({{ Rc = Ra.uq >> Rb_or_imm<5:0>; }}); 21612302Sgabeblack@google.com 0x3c: sra({{ Rc = Ra.sq >> Rb_or_imm<5:0>; }}); 21712302Sgabeblack@google.com 21812302Sgabeblack@google.com 0x02: mskbl({{ Rc = Ra & ~(mask( 8) << (Rb_or_imm<2:0> * 8)); }}); 21912302Sgabeblack@google.com 0x12: mskwl({{ Rc = Ra & ~(mask(16) << (Rb_or_imm<2:0> * 8)); }}); 22012302Sgabeblack@google.com 0x22: mskll({{ Rc = Ra & ~(mask(32) << (Rb_or_imm<2:0> * 8)); }}); 22112302Sgabeblack@google.com 0x32: mskql({{ Rc = Ra & ~(mask(64) << (Rb_or_imm<2:0> * 8)); }}); 22212302Sgabeblack@google.com 22312302Sgabeblack@google.com 0x52: mskwh({{ 22411983Sgabeblack@google.com int bv = Rb_or_imm<2:0>; 22511983Sgabeblack@google.com Rc = bv ? (Ra & ~(mask(16) >> (64 - 8 * bv))) : Ra; 22611983Sgabeblack@google.com }}); 22712302Sgabeblack@google.com 0x62: msklh({{ 22812302Sgabeblack@google.com int bv = Rb_or_imm<2:0>; 22912302Sgabeblack@google.com Rc = bv ? (Ra & ~(mask(32) >> (64 - 8 * bv))) : Ra; 23012302Sgabeblack@google.com }}); 23112302Sgabeblack@google.com 0x72: mskqh({{ 23212302Sgabeblack@google.com int bv = Rb_or_imm<2:0>; 23311983Sgabeblack@google.com Rc = bv ? (Ra & ~(mask(64) >> (64 - 8 * bv))) : Ra; 2346143Snate@binkert.org }}); 23512305Sgabeblack@google.com 23612302Sgabeblack@google.com 0x06: extbl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }}); 23712302Sgabeblack@google.com 0x16: extwl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<15:0>; }}); 23812302Sgabeblack@google.com 0x26: extll({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<31:0>; }}); 2396143Snate@binkert.org 0x36: extql({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8)); }}); 2406143Snate@binkert.org 2416143Snate@binkert.org 0x5a: extwh({{ 2425522Snate@binkert.org Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<15:0>; }}); 2436143Snate@binkert.org 0x6a: extlh({{ 2446143Snate@binkert.org Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<31:0>; }}); 2456143Snate@binkert.org 0x7a: extqh({{ 2469982Satgutier@umich.edu Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>); }}); 24712302Sgabeblack@google.com 24812302Sgabeblack@google.com 0x0b: insbl({{ Rc = Ra< 7:0> << (Rb_or_imm<2:0> * 8); }}); 24912302Sgabeblack@google.com 0x1b: inswl({{ Rc = Ra<15:0> << (Rb_or_imm<2:0> * 8); }}); 2506143Snate@binkert.org 0x2b: insll({{ Rc = Ra<31:0> << (Rb_or_imm<2:0> * 8); }}); 2516143Snate@binkert.org 0x3b: insql({{ Rc = Ra << (Rb_or_imm<2:0> * 8); }}); 2526143Snate@binkert.org 2536143Snate@binkert.org 0x57: inswh({{ 2545522Snate@binkert.org int bv = Rb_or_imm<2:0>; 2555522Snate@binkert.org Rc = bv ? (Ra.uq<15:0> >> (64 - 8 * bv)) : 0; 2565522Snate@binkert.org }}); 2575522Snate@binkert.org 0x67: inslh({{ 2585604Snate@binkert.org int bv = Rb_or_imm<2:0>; 2595604Snate@binkert.org Rc = bv ? (Ra.uq<31:0> >> (64 - 8 * bv)) : 0; 2606143Snate@binkert.org }}); 2616143Snate@binkert.org 0x77: insqh({{ 2624762Snate@binkert.org int bv = Rb_or_imm<2:0>; 2634762Snate@binkert.org Rc = bv ? (Ra.uq >> (64 - 8 * bv)) : 0; 2646143Snate@binkert.org }}); 2656727Ssteve.reinhardt@amd.com 2666727Ssteve.reinhardt@amd.com 0x30: zap({{ 2676727Ssteve.reinhardt@amd.com uint64_t zapmask = 0; 2684762Snate@binkert.org for (int i = 0; i < 8; ++i) { 2696143Snate@binkert.org if (Rb_or_imm<i:>) 2706143Snate@binkert.org zapmask |= (mask(8) << (i * 8)); 2716143Snate@binkert.org } 2726143Snate@binkert.org Rc = Ra & ~zapmask; 2736727Ssteve.reinhardt@amd.com }}); 2746143Snate@binkert.org 0x31: zapnot({{ 2757674Snate@binkert.org uint64_t zapmask = 0; 2767674Snate@binkert.org for (int i = 0; i < 8; ++i) { 2775604Snate@binkert.org if (!Rb_or_imm<i:>) 2786143Snate@binkert.org zapmask |= (mask(8) << (i * 8)); 2796143Snate@binkert.org } 2806143Snate@binkert.org Rc = Ra & ~zapmask; 2814762Snate@binkert.org }}); 2826143Snate@binkert.org } 2834762Snate@binkert.org 2844762Snate@binkert.org 0x13: decode INTFUNC { // integer multiplies 2854762Snate@binkert.org 0x00: mull({{ Rc.sl = Ra.sl * Rb_or_imm.sl; }}, IntMultOp); 2866143Snate@binkert.org 0x20: mulq({{ Rc = Ra * Rb_or_imm; }}, IntMultOp); 2876143Snate@binkert.org 0x30: umulh({{ 2884762Snate@binkert.org uint64_t hi, lo; 28912302Sgabeblack@google.com mul128(Ra, Rb_or_imm, hi, lo); 29012302Sgabeblack@google.com Rc = hi; 2918233Snate@binkert.org }}, IntMultOp); 29212302Sgabeblack@google.com 0x40: mullv({{ 2936143Snate@binkert.org // 32-bit multiply with trap on overflow 2946143Snate@binkert.org int64_t Rax = Ra.sl; // sign extended version of Ra.sl 2954762Snate@binkert.org int64_t Rbx = Rb_or_imm.sl; 2966143Snate@binkert.org int64_t tmp = Rax * Rbx; 2974762Snate@binkert.org // To avoid overflow, all the upper 32 bits must match 2989396Sandreas.hansson@arm.com // the sign bit of the lower 32. We code this as 2999396Sandreas.hansson@arm.com // checking the upper 33 bits for all 0s or all 1s. 3009396Sandreas.hansson@arm.com uint64_t sign_bits = tmp<63:31>; 30112302Sgabeblack@google.com if (sign_bits != 0 && sign_bits != mask(33)) 30212302Sgabeblack@google.com fault = new IntegerOverflowFault; 30312302Sgabeblack@google.com Rc.sl = tmp<31:0>; 3049396Sandreas.hansson@arm.com }}, IntMultOp); 3059396Sandreas.hansson@arm.com 0x60: mulqv({{ 3069396Sandreas.hansson@arm.com // 64-bit multiply with trap on overflow 3079396Sandreas.hansson@arm.com uint64_t hi, lo; 3089396Sandreas.hansson@arm.com mul128(Ra, Rb_or_imm, hi, lo); 3099396Sandreas.hansson@arm.com // all the upper 64 bits must match the sign bit of 3109396Sandreas.hansson@arm.com // the lower 64 3119930Sandreas.hansson@arm.com if (!((hi == 0 && lo<63:> == 0) || 3129930Sandreas.hansson@arm.com (hi == mask(64) && lo<63:> == 1))) 3139396Sandreas.hansson@arm.com fault = new IntegerOverflowFault; 3148235Snate@binkert.org Rc = lo; 3158235Snate@binkert.org }}, IntMultOp); 3166143Snate@binkert.org } 3178235Snate@binkert.org 3189003SAli.Saidi@ARM.com 0x1c: decode INTFUNC { 3198235Snate@binkert.org 0x00: decode RA { 31: sextb({{ Rc.sb = Rb_or_imm< 7:0>; }}); } 3208235Snate@binkert.org 0x01: decode RA { 31: sextw({{ Rc.sw = Rb_or_imm<15:0>; }}); } 32112302Sgabeblack@google.com 0x32: ctlz({{ 3228235Snate@binkert.org uint64_t count = 0; 32312302Sgabeblack@google.com uint64_t temp = Rb; 3248235Snate@binkert.org if (temp<63:32>) temp >>= 32; else count += 32; 3258235Snate@binkert.org if (temp<31:16>) temp >>= 16; else count += 16; 32612302Sgabeblack@google.com if (temp<15:8>) temp >>= 8; else count += 8; 3278235Snate@binkert.org if (temp<7:4>) temp >>= 4; else count += 4; 3288235Snate@binkert.org if (temp<3:2>) temp >>= 2; else count += 2; 3298235Snate@binkert.org if (temp<1:1>) temp >>= 1; else count += 1; 3308235Snate@binkert.org if ((temp<0:0>) != 0x1) count += 1; 3319003SAli.Saidi@ARM.com Rc = count; 33212313Sgabeblack@google.com }}, IntAluOp); 33312313Sgabeblack@google.com 33412313Sgabeblack@google.com 0x33: cttz({{ 33512313Sgabeblack@google.com uint64_t count = 0; 33612313Sgabeblack@google.com uint64_t temp = Rb; 33712315Sgabeblack@google.com if (!(temp<31:0>)) { temp >>= 32; count += 32; } 33812371Sgabeblack@google.com if (!(temp<15:0>)) { temp >>= 16; count += 16; } 33912371Sgabeblack@google.com if (!(temp<7:0>)) { temp >>= 8; count += 8; } 34012371Sgabeblack@google.com if (!(temp<3:0>)) { temp >>= 4; count += 4; } 34112315Sgabeblack@google.com if (!(temp<1:0>)) { temp >>= 2; count += 2; } 34212315Sgabeblack@google.com if (!(temp<0:0> & ULL(0x1))) count += 1; 34312371Sgabeblack@google.com Rc = count; 3445584Snate@binkert.org }}, IntAluOp); 3454382Sbinkertn@umich.edu 3464202Sbinkertn@umich.edu format FailUnimpl { 3474382Sbinkertn@umich.edu 0x30: ctpop(); 3484382Sbinkertn@umich.edu 0x31: perr(); 3499396Sandreas.hansson@arm.com 0x34: unpkbw(); 3505584Snate@binkert.org 0x35: unpkbl(); 35112313Sgabeblack@google.com 0x36: pkwb(); 3524382Sbinkertn@umich.edu 0x37: pklb(); 3534382Sbinkertn@umich.edu 0x38: minsb8(); 3544382Sbinkertn@umich.edu 0x39: minsw4(); 3558232Snate@binkert.org 0x3a: minub8(); 3565192Ssaidi@eecs.umich.edu 0x3b: minuw4(); 3578232Snate@binkert.org 0x3c: maxub8(); 3588232Snate@binkert.org 0x3d: maxuw4(); 3598232Snate@binkert.org 0x3e: maxsb8(); 3605192Ssaidi@eecs.umich.edu 0x3f: maxsw4(); 3618232Snate@binkert.org } 3625192Ssaidi@eecs.umich.edu 3635799Snate@binkert.org format BasicOperateWithNopCheck { 3648232Snate@binkert.org 0x70: decode RB { 3655192Ssaidi@eecs.umich.edu 31: ftoit({{ Rc = Fa.uq; }}, FloatCvtOp); 3665192Ssaidi@eecs.umich.edu } 3675192Ssaidi@eecs.umich.edu 0x78: decode RB { 3688232Snate@binkert.org 31: ftois({{ Rc.sl = t_to_s(Fa.uq); }}, 3695192Ssaidi@eecs.umich.edu FloatCvtOp); 3708232Snate@binkert.org } 3715192Ssaidi@eecs.umich.edu } 3725192Ssaidi@eecs.umich.edu } 3735192Ssaidi@eecs.umich.edu } 3745192Ssaidi@eecs.umich.edu 3754382Sbinkertn@umich.edu // Conditional branches. 3764382Sbinkertn@umich.edu format CondBranch { 3774382Sbinkertn@umich.edu 0x39: beq({{ cond = (Ra == 0); }}); 3782667Sstever@eecs.umich.edu 0x3d: bne({{ cond = (Ra != 0); }}); 3792667Sstever@eecs.umich.edu 0x3e: bge({{ cond = (Ra.sq >= 0); }}); 3802667Sstever@eecs.umich.edu 0x3f: bgt({{ cond = (Ra.sq > 0); }}); 3812667Sstever@eecs.umich.edu 0x3b: ble({{ cond = (Ra.sq <= 0); }}); 3822667Sstever@eecs.umich.edu 0x3a: blt({{ cond = (Ra.sq < 0); }}); 3832667Sstever@eecs.umich.edu 0x38: blbc({{ cond = ((Ra & 1) == 0); }}); 3845742Snate@binkert.org 0x3c: blbs({{ cond = ((Ra & 1) == 1); }}); 3855742Snate@binkert.org 3865742Snate@binkert.org 0x31: fbeq({{ cond = (Fa == 0); }}); 3875793Snate@binkert.org 0x35: fbne({{ cond = (Fa != 0); }}); 3888334Snate@binkert.org 0x36: fbge({{ cond = (Fa >= 0); }}); 3895793Snate@binkert.org 0x37: fbgt({{ cond = (Fa > 0); }}); 3905793Snate@binkert.org 0x33: fble({{ cond = (Fa <= 0); }}); 3915793Snate@binkert.org 0x32: fblt({{ cond = (Fa < 0); }}); 3924382Sbinkertn@umich.edu } 3934762Snate@binkert.org 3945344Sstever@gmail.com // unconditional branches 3954382Sbinkertn@umich.edu format UncondBranch { 3965341Sstever@gmail.com 0x30: br(); 3975742Snate@binkert.org 0x34: bsr(IsCall); 3985742Snate@binkert.org } 3995742Snate@binkert.org 4005742Snate@binkert.org // indirect branches 4015742Snate@binkert.org 0x1a: decode JMPFUNC { 4024762Snate@binkert.org format Jump { 4035742Snate@binkert.org 0: jmp(); 4045742Snate@binkert.org 1: jsr(IsCall); 40511984Sgabeblack@google.com 2: ret(IsReturn); 4067722Sgblack@eecs.umich.edu 3: jsr_coroutine(IsCall, IsReturn); 4075742Snate@binkert.org } 4085742Snate@binkert.org } 4095742Snate@binkert.org 4109930Sandreas.hansson@arm.com // Square root and integer-to-FP moves 4119930Sandreas.hansson@arm.com 0x14: decode FP_SHORTFUNC { 4129930Sandreas.hansson@arm.com // Integer to FP register moves must have RB == 31 4139930Sandreas.hansson@arm.com 0x4: decode RB { 4149930Sandreas.hansson@arm.com 31: decode FP_FULLFUNC { 4155742Snate@binkert.org format BasicOperateWithNopCheck { 4168242Sbradley.danofsky@amd.com 0x004: itofs({{ Fc.uq = s_to_t(Ra.ul); }}, FloatCvtOp); 4178242Sbradley.danofsky@amd.com 0x024: itoft({{ Fc.uq = Ra.uq; }}, FloatCvtOp); 4188242Sbradley.danofsky@amd.com 0x014: FailUnimpl::itoff(); // VAX-format conversion 4198242Sbradley.danofsky@amd.com } 4205341Sstever@gmail.com } 4215742Snate@binkert.org } 4227722Sgblack@eecs.umich.edu 4234773Snate@binkert.org // Square root instructions must have FA == 31 4246108Snate@binkert.org 0xb: decode FA { 4251858SN/A 31: decode FP_TYPEFUNC { 4261085SN/A format FloatingPointOperate { 4276658Snate@binkert.org#if SS_COMPATIBLE_FP 4286658Snate@binkert.org 0x0b: sqrts({{ 4297673Snate@binkert.org if (Fb < 0.0) 4306658Snate@binkert.org fault = new ArithmeticFault; 4316658Snate@binkert.org Fc = sqrt(Fb); 43211308Santhony.gutierrez@amd.com }}, FloatSqrtOp); 4336658Snate@binkert.org#else 43411308Santhony.gutierrez@amd.com 0x0b: sqrts({{ 4356658Snate@binkert.org if (Fb.sf < 0.0) 4366658Snate@binkert.org fault = new ArithmeticFault; 4377673Snate@binkert.org Fc.sf = sqrt(Fb.sf); 4387673Snate@binkert.org }}, FloatSqrtOp); 4397673Snate@binkert.org#endif 4407673Snate@binkert.org 0x2b: sqrtt({{ 4417673Snate@binkert.org if (Fb < 0.0) 4427673Snate@binkert.org fault = new ArithmeticFault; 4437673Snate@binkert.org Fc = sqrt(Fb); 44410467Sandreas.hansson@arm.com }}, FloatSqrtOp); 4456658Snate@binkert.org } 4467673Snate@binkert.org } 44710467Sandreas.hansson@arm.com } 44810467Sandreas.hansson@arm.com 44910467Sandreas.hansson@arm.com // VAX-format sqrtf and sqrtg are not implemented 45010467Sandreas.hansson@arm.com 0xa: FailUnimpl::sqrtfg(); 45110467Sandreas.hansson@arm.com } 45210467Sandreas.hansson@arm.com 45310467Sandreas.hansson@arm.com // IEEE floating point 45410467Sandreas.hansson@arm.com 0x16: decode FP_SHORTFUNC_TOP2 { 45510467Sandreas.hansson@arm.com // The top two bits of the short function code break this 45610467Sandreas.hansson@arm.com // space into four groups: binary ops, compares, reserved, and 45710467Sandreas.hansson@arm.com // conversions. See Table 4-12 of AHB. There are different 4587673Snate@binkert.org // special cases in these different groups, so we decode on 4597673Snate@binkert.org // these top two bits first just to select a decode strategy. 4607673Snate@binkert.org // Most of these instructions may have various trapping and 4617673Snate@binkert.org // rounding mode flags set; these are decoded in the 4627673Snate@binkert.org // FloatingPointDecode template used by the 4639048SAli.Saidi@ARM.com // FloatingPointOperate format. 4647673Snate@binkert.org 4657673Snate@binkert.org // add/sub/mul/div: just decode on the short function code 4667673Snate@binkert.org // and source type. All valid trapping and rounding modes apply. 4677673Snate@binkert.org 0: decode FP_TRAPMODE { 4686658Snate@binkert.org // check for valid trapping modes here 4697756SAli.Saidi@ARM.com 0,1,5,7: decode FP_TYPEFUNC { 4707816Ssteve.reinhardt@amd.com format FloatingPointOperate { 4716658Snate@binkert.org#if SS_COMPATIBLE_FP 47211308Santhony.gutierrez@amd.com 0x00: adds({{ Fc = Fa + Fb; }}); 47311308Santhony.gutierrez@amd.com 0x01: subs({{ Fc = Fa - Fb; }}); 47411308Santhony.gutierrez@amd.com 0x02: muls({{ Fc = Fa * Fb; }}, FloatMultOp); 47511308Santhony.gutierrez@amd.com 0x03: divs({{ Fc = Fa / Fb; }}, FloatDivOp); 47611308Santhony.gutierrez@amd.com#else 47711308Santhony.gutierrez@amd.com 0x00: adds({{ Fc.sf = Fa.sf + Fb.sf; }}); 47811308Santhony.gutierrez@amd.com 0x01: subs({{ Fc.sf = Fa.sf - Fb.sf; }}); 47911308Santhony.gutierrez@amd.com 0x02: muls({{ Fc.sf = Fa.sf * Fb.sf; }}, FloatMultOp); 48011308Santhony.gutierrez@amd.com 0x03: divs({{ Fc.sf = Fa.sf / Fb.sf; }}, FloatDivOp); 48111308Santhony.gutierrez@amd.com#endif 48211308Santhony.gutierrez@amd.com 48311308Santhony.gutierrez@amd.com 0x20: addt({{ Fc = Fa + Fb; }}); 48411308Santhony.gutierrez@amd.com 0x21: subt({{ Fc = Fa - Fb; }}); 48511308Santhony.gutierrez@amd.com 0x22: mult({{ Fc = Fa * Fb; }}, FloatMultOp); 48611308Santhony.gutierrez@amd.com 0x23: divt({{ Fc = Fa / Fb; }}, FloatDivOp); 48711308Santhony.gutierrez@amd.com } 48811308Santhony.gutierrez@amd.com } 48911308Santhony.gutierrez@amd.com } 49011308Santhony.gutierrez@amd.com 49111308Santhony.gutierrez@amd.com // Floating-point compare instructions must have the default 49211308Santhony.gutierrez@amd.com // rounding mode, and may use the default trapping mode or 49311308Santhony.gutierrez@amd.com // /SU. Both trapping modes are treated the same by M5; the 49411308Santhony.gutierrez@amd.com // only difference on the real hardware (as far a I can tell) 49511308Santhony.gutierrez@amd.com // is that without /SU you'd get an imprecise trap if you 49611308Santhony.gutierrez@amd.com // tried to compare a NaN with something else (instead of an 49711308Santhony.gutierrez@amd.com // "unordered" result). 49811308Santhony.gutierrez@amd.com 1: decode FP_FULLFUNC { 49911308Santhony.gutierrez@amd.com format BasicOperateWithNopCheck { 50011308Santhony.gutierrez@amd.com 0x0a5, 0x5a5: cmpteq({{ Fc = (Fa == Fb) ? 2.0 : 0.0; }}, 50111308Santhony.gutierrez@amd.com FloatCmpOp); 50211308Santhony.gutierrez@amd.com 0x0a7, 0x5a7: cmptle({{ Fc = (Fa <= Fb) ? 2.0 : 0.0; }}, 50311308Santhony.gutierrez@amd.com FloatCmpOp); 50411308Santhony.gutierrez@amd.com 0x0a6, 0x5a6: cmptlt({{ Fc = (Fa < Fb) ? 2.0 : 0.0; }}, 50511308Santhony.gutierrez@amd.com FloatCmpOp); 50611308Santhony.gutierrez@amd.com 0x0a4, 0x5a4: cmptun({{ // unordered 50711308Santhony.gutierrez@amd.com Fc = (!(Fa < Fb) && !(Fa == Fb) && !(Fa > Fb)) ? 2.0 : 0.0; 50811308Santhony.gutierrez@amd.com }}, FloatCmpOp); 50911308Santhony.gutierrez@amd.com } 51011308Santhony.gutierrez@amd.com } 51111308Santhony.gutierrez@amd.com 51211308Santhony.gutierrez@amd.com // The FP-to-integer and integer-to-FP conversion insts 51311308Santhony.gutierrez@amd.com // require that FA be 31. 51411308Santhony.gutierrez@amd.com 3: decode FA { 51511308Santhony.gutierrez@amd.com 31: decode FP_TYPEFUNC { 51611308Santhony.gutierrez@amd.com format FloatingPointOperate { 5174382Sbinkertn@umich.edu 0x2f: decode FP_ROUNDMODE { 5184382Sbinkertn@umich.edu format FPFixedRounding { 5194762Snate@binkert.org // "chopped" i.e. round toward zero 5204762Snate@binkert.org 0: cvttq({{ Fc.sq = (int64_t)trunc(Fb); }}, 5214762Snate@binkert.org Chopped); 5226654Snate@binkert.org // round to minus infinity 5236654Snate@binkert.org 1: cvttq({{ Fc.sq = (int64_t)floor(Fb); }}, 5245517Snate@binkert.org MinusInfinity); 5255517Snate@binkert.org } 5265517Snate@binkert.org default: cvttq({{ Fc.sq = (int64_t)nearbyint(Fb); }}); 5275517Snate@binkert.org } 5285517Snate@binkert.org 5295517Snate@binkert.org // The cvtts opcode is overloaded to be cvtst if the trap 5305517Snate@binkert.org // mode is 2 or 6 (which are not valid otherwise) 5315517Snate@binkert.org 0x2c: decode FP_FULLFUNC { 5325517Snate@binkert.org format BasicOperateWithNopCheck { 5335517Snate@binkert.org // trap on denorm version "cvtst/s" is 5345517Snate@binkert.org // simulated same as cvtst 5355517Snate@binkert.org 0x2ac, 0x6ac: cvtst({{ Fc = Fb.sf; }}); 5365517Snate@binkert.org } 5375517Snate@binkert.org default: cvtts({{ Fc.sf = Fb; }}); 5385517Snate@binkert.org } 5395517Snate@binkert.org 5405517Snate@binkert.org // The trapping mode for integer-to-FP conversions 5416654Snate@binkert.org // must be /SUI or nothing; /U and /SU are not 5425517Snate@binkert.org // allowed. The full set of rounding modes are 5435517Snate@binkert.org // supported though. 5445517Snate@binkert.org 0x3c: decode FP_TRAPMODE { 5455517Snate@binkert.org 0,7: cvtqs({{ Fc.sf = Fb.sq; }}); 5465517Snate@binkert.org } 54711802Sandreas.sandberg@arm.com 0x3e: decode FP_TRAPMODE { 5485517Snate@binkert.org 0,7: cvtqt({{ Fc = Fb.sq; }}); 5495517Snate@binkert.org } 5506143Snate@binkert.org } 5516654Snate@binkert.org } 5525517Snate@binkert.org } 5535517Snate@binkert.org } 5545517Snate@binkert.org 5555517Snate@binkert.org // misc FP operate 5565517Snate@binkert.org 0x17: decode FP_FULLFUNC { 5575517Snate@binkert.org format BasicOperateWithNopCheck { 5585517Snate@binkert.org 0x010: cvtlq({{ 5595517Snate@binkert.org Fc.sl = (Fb.uq<63:62> << 30) | Fb.uq<58:29>; 5605517Snate@binkert.org }}); 5615517Snate@binkert.org 0x030: cvtql({{ 5625517Snate@binkert.org Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29); 5635517Snate@binkert.org }}); 5645517Snate@binkert.org 5655517Snate@binkert.org // We treat the precise & imprecise trapping versions of 5666654Snate@binkert.org // cvtql identically. 5676654Snate@binkert.org 0x130, 0x530: cvtqlv({{ 5685517Snate@binkert.org // To avoid overflow, all the upper 32 bits must match 5695517Snate@binkert.org // the sign bit of the lower 32. We code this as 5706143Snate@binkert.org // checking the upper 33 bits for all 0s or all 1s. 5716143Snate@binkert.org uint64_t sign_bits = Fb.uq<63:31>; 5726143Snate@binkert.org if (sign_bits != 0 && sign_bits != mask(33)) 5736727Ssteve.reinhardt@amd.com fault = new IntegerOverflowFault; 5745517Snate@binkert.org Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29); 5756727Ssteve.reinhardt@amd.com }}); 5765517Snate@binkert.org 5775517Snate@binkert.org 0x020: cpys({{ // copy sign 5785517Snate@binkert.org Fc.uq = (Fa.uq<63:> << 63) | Fb.uq<62:0>; 5796654Snate@binkert.org }}); 5806654Snate@binkert.org 0x021: cpysn({{ // copy sign negated 5817673Snate@binkert.org Fc.uq = (~Fa.uq<63:> << 63) | Fb.uq<62:0>; 5826654Snate@binkert.org }}); 5836654Snate@binkert.org 0x022: cpyse({{ // copy sign and exponent 5846654Snate@binkert.org Fc.uq = (Fa.uq<63:52> << 52) | Fb.uq<51:0>; 5856654Snate@binkert.org }}); 5865517Snate@binkert.org 5875517Snate@binkert.org 0x02a: fcmoveq({{ Fc = (Fa == 0) ? Fb : Fc; }}); 5885517Snate@binkert.org 0x02b: fcmovne({{ Fc = (Fa != 0) ? Fb : Fc; }}); 5896143Snate@binkert.org 0x02c: fcmovlt({{ Fc = (Fa < 0) ? Fb : Fc; }}); 5905517Snate@binkert.org 0x02d: fcmovge({{ Fc = (Fa >= 0) ? Fb : Fc; }}); 5914762Snate@binkert.org 0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }}); 5925517Snate@binkert.org 0x02f: fcmovgt({{ Fc = (Fa > 0) ? Fb : Fc; }}); 5935517Snate@binkert.org 5946143Snate@binkert.org 0x024: mt_fpcr({{ FPCR = Fa.uq; }}); 5956143Snate@binkert.org 0x025: mf_fpcr({{ Fa.uq = FPCR; }}); 5965517Snate@binkert.org } 5975517Snate@binkert.org } 5985517Snate@binkert.org 5995517Snate@binkert.org // miscellaneous mem-format ops 6005517Snate@binkert.org 0x18: decode MEMFUNC { 6015517Snate@binkert.org format WarnUnimpl { 6025517Snate@binkert.org 0x8000: fetch(); 6035517Snate@binkert.org 0xa000: fetch_m(); 6045517Snate@binkert.org 0xe800: ecb(); 6056143Snate@binkert.org } 6065517Snate@binkert.org 6076654Snate@binkert.org format MiscPrefetch { 6086654Snate@binkert.org 0xf800: wh64({{ EA = Rb & ~ULL(63); }}, 6096654Snate@binkert.org {{ xc->writeHint(EA, 64, memAccessFlags); }}, 6106654Snate@binkert.org mem_flags = NO_FAULT, 6116654Snate@binkert.org inst_flags = [IsMemRef, IsDataPrefetch, 6126654Snate@binkert.org IsStore, MemWriteOp]); 6134762Snate@binkert.org } 6144762Snate@binkert.org 6154762Snate@binkert.org format BasicOperate { 6164762Snate@binkert.org 0xc000: rpcc({{ 6174762Snate@binkert.org#if FULL_SYSTEM 6187675Snate@binkert.org /* Rb is a fake dependency so here is a fun way to get 61910584Sandreas.hansson@arm.com * the parser to understand that. 6204762Snate@binkert.org */ 6214762Snate@binkert.org Ra = xc->readMiscRegWithEffect(AlphaISA::IPR_CC, fault) + (Rb & 0); 6224762Snate@binkert.org 6234762Snate@binkert.org#else 6244382Sbinkertn@umich.edu Ra = curTick; 6254382Sbinkertn@umich.edu#endif 6265517Snate@binkert.org }}); 6276654Snate@binkert.org 6285517Snate@binkert.org // All of the barrier instructions below do nothing in 6298126Sgblack@eecs.umich.edu // their execute() methods (hence the empty code blocks). 6306654Snate@binkert.org // All of their functionality is hard-coded in the 6317673Snate@binkert.org // pipeline based on the flags IsSerializing, 6326654Snate@binkert.org // IsMemBarrier, and IsWriteBarrier. In the current 63311802Sandreas.sandberg@arm.com // detailed CPU model, the execute() function only gets 6346654Snate@binkert.org // called at fetch, so there's no way to generate pipeline 6356654Snate@binkert.org // behavior at any other stage. Once we go to an 6366654Snate@binkert.org // exec-in-exec CPU model we should be able to get rid of 6376654Snate@binkert.org // these flags and implement this behavior via the 63811802Sandreas.sandberg@arm.com // execute() methods. 6396669Snate@binkert.org 64011802Sandreas.sandberg@arm.com // trapb is just a barrier on integer traps, where excb is 6416669Snate@binkert.org // a barrier on integer and FP traps. "EXCB is thus a 6426669Snate@binkert.org // superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat 6436669Snate@binkert.org // them the same though. 6446669Snate@binkert.org 0x0000: trapb({{ }}, IsSerializing, No_OpClass); 6456654Snate@binkert.org 0x0400: excb({{ }}, IsSerializing, No_OpClass); 6467673Snate@binkert.org 0x4000: mb({{ }}, IsMemBarrier, MemReadOp); 6475517Snate@binkert.org 0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp); 6488126Sgblack@eecs.umich.edu } 6495798Snate@binkert.org 6507756SAli.Saidi@ARM.com#if FULL_SYSTEM 6517816Ssteve.reinhardt@amd.com format BasicOperate { 6525798Snate@binkert.org 0xe000: rc({{ 6535798Snate@binkert.org Ra = xc->readIntrFlag(); 6545517Snate@binkert.org xc->setIntrFlag(0); 6555517Snate@binkert.org }}, IsNonSpeculative); 6567673Snate@binkert.org 0xf000: rs({{ 6575517Snate@binkert.org Ra = xc->readIntrFlag(); 6585517Snate@binkert.org xc->setIntrFlag(1); 6597673Snate@binkert.org }}, IsNonSpeculative); 6607673Snate@binkert.org } 6615517Snate@binkert.org#else 6625798Snate@binkert.org format FailUnimpl { 6635798Snate@binkert.org 0xe000: rc(); 6648333Snate@binkert.org 0xf000: rs(); 6657816Ssteve.reinhardt@amd.com } 6665798Snate@binkert.org#endif 6675798Snate@binkert.org } 6684762Snate@binkert.org 6694762Snate@binkert.org#if FULL_SYSTEM 6704762Snate@binkert.org 0x00: CallPal::call_pal({{ 6714762Snate@binkert.org if (!palValid || 6724762Snate@binkert.org (palPriv 6738596Ssteve.reinhardt@amd.com && xc->readMiscRegWithEffect(AlphaISA::IPR_ICM, fault) != AlphaISA::mode_kernel)) { 6745517Snate@binkert.org // invalid pal function code, or attempt to do privileged 6755517Snate@binkert.org // PAL call in non-kernel mode 67611997Sgabeblack@google.com fault = new UnimplementedOpcodeFault; 6775517Snate@binkert.org } 6785517Snate@binkert.org else { 6797673Snate@binkert.org // check to see if simulator wants to do something special 6808596Ssteve.reinhardt@amd.com // on this PAL call (including maybe suppress it) 6817673Snate@binkert.org bool dopal = xc->simPalCheck(palFunc); 6825517Snate@binkert.org 68310458Sandreas.hansson@arm.com if (dopal) { 68410458Sandreas.hansson@arm.com xc->setMiscRegWithEffect(AlphaISA::IPR_EXC_ADDR, NPC); 68510458Sandreas.hansson@arm.com NPC = xc->readMiscRegWithEffect(AlphaISA::IPR_PAL_BASE, fault) + palOffset; 68610458Sandreas.hansson@arm.com } 68710458Sandreas.hansson@arm.com } 68810458Sandreas.hansson@arm.com }}, IsNonSpeculative); 68910458Sandreas.hansson@arm.com#else 69010458Sandreas.hansson@arm.com 0x00: decode PALFUNC { 69110458Sandreas.hansson@arm.com format EmulatedCallPal { 69210458Sandreas.hansson@arm.com 0x00: halt ({{ 69310458Sandreas.hansson@arm.com SimExit(curTick, "halt instruction encountered"); 69410458Sandreas.hansson@arm.com }}, IsNonSpeculative); 6955517Snate@binkert.org 0x83: callsys({{ 69611996Sgabeblack@google.com xc->syscall(); 6975517Snate@binkert.org }}, IsNonSpeculative); 69811997Sgabeblack@google.com // Read uniq reg into ABI return value register (r0) 69911996Sgabeblack@google.com 0x9e: rduniq({{ R0 = Runiq; }}); 7005517Snate@binkert.org // Write uniq reg with value from ABI arg register (r16) 7015517Snate@binkert.org 0x9f: wruniq({{ Runiq = R16; }}); 7027673Snate@binkert.org } 7037673Snate@binkert.org } 70411996Sgabeblack@google.com#endif 70511988Sandreas.sandberg@arm.com 7067673Snate@binkert.org#if FULL_SYSTEM 7075517Snate@binkert.org 0x1b: decode PALMODE { 7088596Ssteve.reinhardt@amd.com 0: OpcdecFault::hw_st_quad(); 7095517Snate@binkert.org 1: decode HW_LDST_QUAD { 7105517Snate@binkert.org format HwLoad { 71111997Sgabeblack@google.com 0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }}, L); 7125517Snate@binkert.org 1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }}, Q); 7135517Snate@binkert.org } 7147673Snate@binkert.org } 7157673Snate@binkert.org } 7167673Snate@binkert.org 7175517Snate@binkert.org 0x1f: decode PALMODE { 71811988Sandreas.sandberg@arm.com 0: OpcdecFault::hw_st_cond(); 71911997Sgabeblack@google.com format HwStore { 7208596Ssteve.reinhardt@amd.com 1: decode HW_LDST_COND { 7218596Ssteve.reinhardt@amd.com 0: decode HW_LDST_QUAD { 7228596Ssteve.reinhardt@amd.com 0: hw_st({{ EA = (Rb + disp) & ~3; }}, 72311988Sandreas.sandberg@arm.com {{ Mem.ul = Ra<31:0>; }}, L); 7248596Ssteve.reinhardt@amd.com 1: hw_st({{ EA = (Rb + disp) & ~7; }}, 7258596Ssteve.reinhardt@amd.com {{ Mem.uq = Ra.uq; }}, Q); 7268596Ssteve.reinhardt@amd.com } 7274762Snate@binkert.org 7286143Snate@binkert.org 1: FailUnimpl::hw_st_cond(); 7296143Snate@binkert.org } 7306143Snate@binkert.org } 7314762Snate@binkert.org } 7324762Snate@binkert.org 7334762Snate@binkert.org 0x19: decode PALMODE { 7347756SAli.Saidi@ARM.com 0: OpcdecFault::hw_mfpr(); 7358596Ssteve.reinhardt@amd.com format HwMoveIPR { 7364762Snate@binkert.org 1: hw_mfpr({{ 7374762Snate@binkert.org Ra = xc->readMiscRegWithEffect(ipr_index, fault); 73810458Sandreas.hansson@arm.com }}); 73910458Sandreas.hansson@arm.com } 74010458Sandreas.hansson@arm.com } 74110458Sandreas.hansson@arm.com 74210458Sandreas.hansson@arm.com 0x1d: decode PALMODE { 74310458Sandreas.hansson@arm.com 0: OpcdecFault::hw_mtpr(); 74410458Sandreas.hansson@arm.com format HwMoveIPR { 74510458Sandreas.hansson@arm.com 1: hw_mtpr({{ 74610458Sandreas.hansson@arm.com xc->setMiscRegWithEffect(ipr_index, Ra); 74710458Sandreas.hansson@arm.com if (traceData) { traceData->setData(Ra); } 74810458Sandreas.hansson@arm.com }}); 74910458Sandreas.hansson@arm.com } 75010458Sandreas.hansson@arm.com } 75110458Sandreas.hansson@arm.com 75210458Sandreas.hansson@arm.com format BasicOperate { 75310458Sandreas.hansson@arm.com 0x1e: decode PALMODE { 75410458Sandreas.hansson@arm.com 0: OpcdecFault::hw_rei(); 75510458Sandreas.hansson@arm.com 1:hw_rei({{ xc->hwrei(); }}, IsSerializing); 75610458Sandreas.hansson@arm.com } 75710458Sandreas.hansson@arm.com 75810458Sandreas.hansson@arm.com // M5 special opcodes use the reserved 0x01 opcode space 75910458Sandreas.hansson@arm.com 0x01: decode M5FUNC { 76010458Sandreas.hansson@arm.com 0x00: arm({{ 76110458Sandreas.hansson@arm.com AlphaPseudo::arm(xc->xcBase()); 76210458Sandreas.hansson@arm.com }}, IsNonSpeculative); 76310458Sandreas.hansson@arm.com 0x01: quiesce({{ 76410458Sandreas.hansson@arm.com AlphaPseudo::quiesce(xc->xcBase()); 76510458Sandreas.hansson@arm.com }}, IsNonSpeculative); 76610458Sandreas.hansson@arm.com 0x02: quiesceNs({{ 76710458Sandreas.hansson@arm.com AlphaPseudo::quiesceNs(xc->xcBase(), R16); 76810458Sandreas.hansson@arm.com }}, IsNonSpeculative); 76910458Sandreas.hansson@arm.com 0x03: quiesceCycles({{ 77010458Sandreas.hansson@arm.com AlphaPseudo::quiesceCycles(xc->xcBase(), R16); 77110458Sandreas.hansson@arm.com }}, IsNonSpeculative); 77210458Sandreas.hansson@arm.com 0x04: quiesceTime({{ 77310458Sandreas.hansson@arm.com R0 = AlphaPseudo::quiesceTime(xc->xcBase()); 77410458Sandreas.hansson@arm.com }}, IsNonSpeculative); 77510458Sandreas.hansson@arm.com 0x10: ivlb({{ 77610458Sandreas.hansson@arm.com AlphaPseudo::ivlb(xc->xcBase()); 77710458Sandreas.hansson@arm.com }}, No_OpClass, IsNonSpeculative); 77810458Sandreas.hansson@arm.com 0x11: ivle({{ 77910458Sandreas.hansson@arm.com AlphaPseudo::ivle(xc->xcBase()); 78010458Sandreas.hansson@arm.com }}, No_OpClass, IsNonSpeculative); 78110458Sandreas.hansson@arm.com 0x20: m5exit_old({{ 78210458Sandreas.hansson@arm.com AlphaPseudo::m5exit_old(xc->xcBase()); 78310458Sandreas.hansson@arm.com }}, No_OpClass, IsNonSpeculative); 78410458Sandreas.hansson@arm.com 0x21: m5exit({{ 78510458Sandreas.hansson@arm.com AlphaPseudo::m5exit(xc->xcBase(), R16); 78610458Sandreas.hansson@arm.com }}, No_OpClass, IsNonSpeculative); 78710584Sandreas.hansson@arm.com 0x30: initparam({{ Ra = xc->xcBase()->getCpuPtr()->system->init_param; }}); 78810458Sandreas.hansson@arm.com 0x40: resetstats({{ 78910458Sandreas.hansson@arm.com AlphaPseudo::resetstats(xc->xcBase(), R16, R17); 79010458Sandreas.hansson@arm.com }}, IsNonSpeculative); 79110458Sandreas.hansson@arm.com 0x41: dumpstats({{ 79210458Sandreas.hansson@arm.com AlphaPseudo::dumpstats(xc->xcBase(), R16, R17); 7934762Snate@binkert.org }}, IsNonSpeculative); 7946143Snate@binkert.org 0x42: dumpresetstats({{ 7956143Snate@binkert.org AlphaPseudo::dumpresetstats(xc->xcBase(), R16, R17); 7966143Snate@binkert.org }}, IsNonSpeculative); 7974762Snate@binkert.org 0x43: m5checkpoint({{ 7984762Snate@binkert.org AlphaPseudo::m5checkpoint(xc->xcBase(), R16, R17); 79911996Sgabeblack@google.com }}, IsNonSpeculative); 8007816Ssteve.reinhardt@amd.com 0x50: m5readfile({{ 8014762Snate@binkert.org R0 = AlphaPseudo::readfile(xc->xcBase(), R16, R17, R18); 8024762Snate@binkert.org }}, IsNonSpeculative); 8034762Snate@binkert.org 0x51: m5break({{ 8044762Snate@binkert.org AlphaPseudo::debugbreak(xc->xcBase()); 8057756SAli.Saidi@ARM.com }}, IsNonSpeculative); 8068596Ssteve.reinhardt@amd.com 0x52: m5switchcpu({{ 8074762Snate@binkert.org AlphaPseudo::switchcpu(xc->xcBase()); 8084762Snate@binkert.org }}, IsNonSpeculative); 80911988Sandreas.sandberg@arm.com 0x53: m5addsymbol({{ 81011988Sandreas.sandberg@arm.com AlphaPseudo::addsymbol(xc->xcBase(), R16, R17); 81111988Sandreas.sandberg@arm.com }}, IsNonSpeculative); 81211988Sandreas.sandberg@arm.com 0x54: m5panic({{ 81311988Sandreas.sandberg@arm.com panic("M5 panic instruction called at pc=%#x.", xc->readPC()); 81411988Sandreas.sandberg@arm.com }}, IsNonSpeculative); 81511988Sandreas.sandberg@arm.com 81611988Sandreas.sandberg@arm.com } 81711988Sandreas.sandberg@arm.com } 81811988Sandreas.sandberg@arm.com#endif 81911988Sandreas.sandberg@arm.com} 8204382Sbinkertn@umich.edu