decoder.isa revision 2284
12SN/A// -*- mode:c++ -*- 211147Smitch.hayenga@arm.com 39920Syasuko.eckert@amd.com// Copyright (c) 2003-2006 The Regents of The University of Michigan 47338SAli.Saidi@ARM.com// All rights reserved. 57338SAli.Saidi@ARM.com// 67338SAli.Saidi@ARM.com// Redistribution and use in source and binary forms, with or without 77338SAli.Saidi@ARM.com// modification, are permitted provided that the following conditions are 87338SAli.Saidi@ARM.com// met: redistributions of source code must retain the above copyright 97338SAli.Saidi@ARM.com// notice, this list of conditions and the following disclaimer; 107338SAli.Saidi@ARM.com// redistributions in binary form must reproduce the above copyright 117338SAli.Saidi@ARM.com// notice, this list of conditions and the following disclaimer in the 127338SAli.Saidi@ARM.com// documentation and/or other materials provided with the distribution; 137338SAli.Saidi@ARM.com// neither the name of the copyright holders nor the names of its 147338SAli.Saidi@ARM.com// contributors may be used to endorse or promote products derived from 151762SN/A// this software without specific prior written permission. 162SN/A// 172SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282SN/A 292SN/Adecode OPCODE default Unknown::unknown() { 302SN/A 312SN/A format LoadAddress { 322SN/A 0x08: lda({{ Ra = Rb + disp; }}); 332SN/A 0x09: ldah({{ Ra = Rb + (disp << 16); }}); 342SN/A } 352SN/A 362SN/A format LoadOrNop { 372SN/A 0x0a: ldbu({{ Ra.uq = Mem.ub; }}); 382SN/A 0x0c: ldwu({{ Ra.uq = Mem.uw; }}); 392SN/A 0x0b: ldq_u({{ Ra = Mem.uq; }}, ea_code = {{ EA = (Rb + disp) & ~7; }}); 402665Ssaidi@eecs.umich.edu 0x23: ldt({{ Fa = Mem.df; }}); 412665Ssaidi@eecs.umich.edu 0x2a: ldl_l({{ Ra.sl = Mem.sl; }}, mem_flags = LOCKED); 422SN/A 0x2b: ldq_l({{ Ra.uq = Mem.uq; }}, mem_flags = LOCKED); 432SN/A 0x20: MiscPrefetch::copy_load({{ EA = Ra; }}, 448779Sgblack@eecs.umich.edu {{ fault = xc->copySrcTranslate(EA); }}, 458779Sgblack@eecs.umich.edu inst_flags = [IsMemRef, IsLoad, IsCopy]); 468779Sgblack@eecs.umich.edu } 472439SN/A 488779Sgblack@eecs.umich.edu format LoadOrPrefetch { 498229Snate@binkert.org 0x28: ldl({{ Ra.sl = Mem.sl; }}); 506216Snate@binkert.org 0x29: ldq({{ Ra.uq = Mem.uq; }}, pf_flags = EVICT_NEXT); 51146SN/A // IsFloating flag on lds gets the prefetch to disassemble 52146SN/A // using f31 instead of r31... funcitonally it's unnecessary 53146SN/A 0x22: lds({{ Fa.uq = s_to_t(Mem.ul); }}, 54146SN/A pf_flags = PF_EXCLUSIVE, inst_flags = IsFloating); 55146SN/A } 566216Snate@binkert.org 576658Snate@binkert.org format Store { 588229Snate@binkert.org 0x0e: stb({{ Mem.ub = Ra<7:0>; }}); 591717SN/A 0x0d: stw({{ Mem.uw = Ra<15:0>; }}); 608887Sgeoffrey.blake@arm.com 0x2c: stl({{ Mem.ul = Ra<31:0>; }}); 618887Sgeoffrey.blake@arm.com 0x2d: stq({{ Mem.uq = Ra.uq; }}); 62146SN/A 0x0f: stq_u({{ Mem.uq = Ra.uq; }}, {{ EA = (Rb + disp) & ~7; }}); 6310061Sandreas@sandberg.pp.se 0x26: sts({{ Mem.ul = t_to_s(Fa.uq); }}); 641977SN/A 0x27: stt({{ Mem.df = Fa; }}); 6511147Smitch.hayenga@arm.com 0x24: MiscPrefetch::copy_store({{ EA = Rb; }}, 662683Sktlim@umich.edu {{ fault = xc->copy(EA); }}, 671717SN/A inst_flags = [IsMemRef, IsStore, IsCopy]); 68146SN/A } 692683Sktlim@umich.edu 708232Snate@binkert.org format StoreCond { 718232Snate@binkert.org 0x2e: stl_c({{ Mem.ul = Ra<31:0>; }}, 728232Snate@binkert.org {{ 738779Sgblack@eecs.umich.edu uint64_t tmp = write_result; 743348Sbinkertn@umich.edu // see stq_c 756105Ssteve.reinhardt@amd.com Ra = (tmp == 0 || tmp == 1) ? tmp : Ra; 766216Snate@binkert.org }}, mem_flags = LOCKED); 772036SN/A 0x2f: stq_c({{ Mem.uq = Ra; }}, 78146SN/A {{ 798817Sgblack@eecs.umich.edu uint64_t tmp = write_result; 808793Sgblack@eecs.umich.edu // If the write operation returns 0 or 1, then 8156SN/A // this was a conventional store conditional, 8256SN/A // and the value indicates the success/failure 83695SN/A // of the operation. If another value is 842901Ssaidi@eecs.umich.edu // returned, then this was a Turbolaser 852SN/A // mailbox access, and we don't update the 862SN/A // result register at all. 872449SN/A Ra = (tmp == 0 || tmp == 1) ? tmp : Ra; 881355SN/A }}, mem_flags = LOCKED); 895529Snate@binkert.org } 9010061Sandreas@sandberg.pp.se 9111147Smitch.hayenga@arm.com format IntegerOperate { 9210061Sandreas@sandberg.pp.se 9311147Smitch.hayenga@arm.com 0x10: decode INTFUNC { // integer arithmetic operations 9411147Smitch.hayenga@arm.com 9511147Smitch.hayenga@arm.com 0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }}); 96224SN/A 0x40: addlv({{ 9711147Smitch.hayenga@arm.com uint32_t tmp = Ra.sl + Rb_or_imm.sl; 982SN/A // signed overflow occurs when operands have same sign 9911147Smitch.hayenga@arm.com // and sign of result does not match. 10011147Smitch.hayenga@arm.com if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>) 10111147Smitch.hayenga@arm.com fault = new IntegerOverflowFault; 10211147Smitch.hayenga@arm.com Rc.sl = tmp; 10311147Smitch.hayenga@arm.com }}); 10411147Smitch.hayenga@arm.com 0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }}); 10511147Smitch.hayenga@arm.com 0x12: s8addl({{ Rc.sl = (Ra.sl << 3) + Rb_or_imm.sl; }}); 10611147Smitch.hayenga@arm.com 10711147Smitch.hayenga@arm.com 0x20: addq({{ Rc = Ra + Rb_or_imm; }}); 10811147Smitch.hayenga@arm.com 0x60: addqv({{ 10911147Smitch.hayenga@arm.com uint64_t tmp = Ra + Rb_or_imm; 11011147Smitch.hayenga@arm.com // signed overflow occurs when operands have same sign 1112SN/A // and sign of result does not match. 1128733Sgeoffrey.blake@arm.com if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>) 11311147Smitch.hayenga@arm.com fault = new IntegerOverflowFault; 11411147Smitch.hayenga@arm.com Rc = tmp; 11511147Smitch.hayenga@arm.com }}); 1168733Sgeoffrey.blake@arm.com 0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }}); 1178733Sgeoffrey.blake@arm.com 0x32: s8addq({{ Rc = (Ra << 3) + Rb_or_imm; }}); 1188733Sgeoffrey.blake@arm.com 1198733Sgeoffrey.blake@arm.com 0x09: subl({{ Rc.sl = Ra.sl - Rb_or_imm.sl; }}); 12011147Smitch.hayenga@arm.com 0x49: sublv({{ 12111147Smitch.hayenga@arm.com uint32_t tmp = Ra.sl - Rb_or_imm.sl; 1228733Sgeoffrey.blake@arm.com // signed overflow detection is same as for add, 1238733Sgeoffrey.blake@arm.com // except we need to look at the *complemented* 1248733Sgeoffrey.blake@arm.com // sign bit of the subtrahend (Rb), i.e., if the initial 12511147Smitch.hayenga@arm.com // signs are the *same* then no overflow can occur 1268733Sgeoffrey.blake@arm.com if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>) 12711147Smitch.hayenga@arm.com fault = new IntegerOverflowFault; 12811147Smitch.hayenga@arm.com Rc.sl = tmp; 12911147Smitch.hayenga@arm.com }}); 13011147Smitch.hayenga@arm.com 0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }}); 1312SN/A 0x1b: s8subl({{ Rc.sl = (Ra.sl << 3) - Rb_or_imm.sl; }}); 13211147Smitch.hayenga@arm.com 13311147Smitch.hayenga@arm.com 0x29: subq({{ Rc = Ra - Rb_or_imm; }}); 13411147Smitch.hayenga@arm.com 0x69: subqv({{ 1354377Sgblack@eecs.umich.edu uint64_t tmp = Ra - Rb_or_imm; 13611147Smitch.hayenga@arm.com // signed overflow detection is same as for add, 13711147Smitch.hayenga@arm.com // except we need to look at the *complemented* 13811147Smitch.hayenga@arm.com // sign bit of the subtrahend (Rb), i.e., if the initial 13911147Smitch.hayenga@arm.com // signs are the *same* then no overflow can occur 14011147Smitch.hayenga@arm.com if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>) 14111147Smitch.hayenga@arm.com fault = new IntegerOverflowFault; 1425169Ssaidi@eecs.umich.edu Rc = tmp; 14311147Smitch.hayenga@arm.com }}); 14411147Smitch.hayenga@arm.com 0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }}); 14511147Smitch.hayenga@arm.com 0x3b: s8subq({{ Rc = (Ra << 3) - Rb_or_imm; }}); 14611147Smitch.hayenga@arm.com 14711147Smitch.hayenga@arm.com 0x2d: cmpeq({{ Rc = (Ra == Rb_or_imm); }}); 14811147Smitch.hayenga@arm.com 0x6d: cmple({{ Rc = (Ra.sq <= Rb_or_imm.sq); }}); 14911147Smitch.hayenga@arm.com 0x4d: cmplt({{ Rc = (Ra.sq < Rb_or_imm.sq); }}); 15011147Smitch.hayenga@arm.com 0x3d: cmpule({{ Rc = (Ra.uq <= Rb_or_imm.uq); }}); 15111147Smitch.hayenga@arm.com 0x1d: cmpult({{ Rc = (Ra.uq < Rb_or_imm.uq); }}); 15211147Smitch.hayenga@arm.com 15311147Smitch.hayenga@arm.com 0x0f: cmpbge({{ 15411147Smitch.hayenga@arm.com int hi = 7; 15511147Smitch.hayenga@arm.com int lo = 0; 15611147Smitch.hayenga@arm.com uint64_t tmp = 0; 15711147Smitch.hayenga@arm.com for (int i = 0; i < 8; ++i) { 15811147Smitch.hayenga@arm.com tmp |= (Ra.uq<hi:lo> >= Rb_or_imm.uq<hi:lo>) << i; 15911147Smitch.hayenga@arm.com hi += 8; 16011147Smitch.hayenga@arm.com lo += 8; 16111147Smitch.hayenga@arm.com } 16211147Smitch.hayenga@arm.com Rc = tmp; 16311147Smitch.hayenga@arm.com }}); 16411147Smitch.hayenga@arm.com } 16511147Smitch.hayenga@arm.com 16611147Smitch.hayenga@arm.com 0x11: decode INTFUNC { // integer logical operations 16711147Smitch.hayenga@arm.com 16811147Smitch.hayenga@arm.com 0x00: and({{ Rc = Ra & Rb_or_imm; }}); 16911147Smitch.hayenga@arm.com 0x08: bic({{ Rc = Ra & ~Rb_or_imm; }}); 17011147Smitch.hayenga@arm.com 0x20: bis({{ Rc = Ra | Rb_or_imm; }}); 17111147Smitch.hayenga@arm.com 0x28: ornot({{ Rc = Ra | ~Rb_or_imm; }}); 17211147Smitch.hayenga@arm.com 0x40: xor({{ Rc = Ra ^ Rb_or_imm; }}); 17311147Smitch.hayenga@arm.com 0x48: eqv({{ Rc = Ra ^ ~Rb_or_imm; }}); 17411147Smitch.hayenga@arm.com 17511147Smitch.hayenga@arm.com // conditional moves 17611147Smitch.hayenga@arm.com 0x14: cmovlbs({{ Rc = ((Ra & 1) == 1) ? Rb_or_imm : Rc; }}); 17711147Smitch.hayenga@arm.com 0x16: cmovlbc({{ Rc = ((Ra & 1) == 0) ? Rb_or_imm : Rc; }}); 17811147Smitch.hayenga@arm.com 0x24: cmoveq({{ Rc = (Ra == 0) ? Rb_or_imm : Rc; }}); 17911147Smitch.hayenga@arm.com 0x26: cmovne({{ Rc = (Ra != 0) ? Rb_or_imm : Rc; }}); 18011147Smitch.hayenga@arm.com 0x44: cmovlt({{ Rc = (Ra.sq < 0) ? Rb_or_imm : Rc; }}); 18111147Smitch.hayenga@arm.com 0x46: cmovge({{ Rc = (Ra.sq >= 0) ? Rb_or_imm : Rc; }}); 18211147Smitch.hayenga@arm.com 0x64: cmovle({{ Rc = (Ra.sq <= 0) ? Rb_or_imm : Rc; }}); 18311147Smitch.hayenga@arm.com 0x66: cmovgt({{ Rc = (Ra.sq > 0) ? Rb_or_imm : Rc; }}); 18411147Smitch.hayenga@arm.com 18511147Smitch.hayenga@arm.com // For AMASK, RA must be R31. 18611147Smitch.hayenga@arm.com 0x61: decode RA { 18711147Smitch.hayenga@arm.com 31: amask({{ Rc = Rb_or_imm & ~ULL(0x17); }}); 18811147Smitch.hayenga@arm.com } 18911147Smitch.hayenga@arm.com 19011147Smitch.hayenga@arm.com // For IMPLVER, RA must be R31 and the B operand 19111147Smitch.hayenga@arm.com // must be the immediate value 1. 19211147Smitch.hayenga@arm.com 0x6c: decode RA { 19311147Smitch.hayenga@arm.com 31: decode IMM { 19411147Smitch.hayenga@arm.com 1: decode INTIMM { 19511147Smitch.hayenga@arm.com // return EV5 for FULL_SYSTEM and EV6 otherwise 19611147Smitch.hayenga@arm.com 1: implver({{ 19711147Smitch.hayenga@arm.com#if FULL_SYSTEM 19811147Smitch.hayenga@arm.com Rc = 1; 19911147Smitch.hayenga@arm.com#else 20011147Smitch.hayenga@arm.com Rc = 2; 20111147Smitch.hayenga@arm.com#endif 20211147Smitch.hayenga@arm.com }}); 20311147Smitch.hayenga@arm.com } 20411147Smitch.hayenga@arm.com } 20511147Smitch.hayenga@arm.com } 2062SN/A 2072SN/A#if FULL_SYSTEM 2082623SN/A // The mysterious 11.25... 2092SN/A 0x25: WarnUnimpl::eleven25(); 2102SN/A#endif 2112SN/A } 212180SN/A 2138737Skoansin.tan@gmail.com 0x12: decode INTFUNC { 214393SN/A 0x39: sll({{ Rc = Ra << Rb_or_imm<5:0>; }}); 215393SN/A 0x34: srl({{ Rc = Ra.uq >> Rb_or_imm<5:0>; }}); 216393SN/A 0x3c: sra({{ Rc = Ra.sq >> Rb_or_imm<5:0>; }}); 217393SN/A 218384SN/A 0x02: mskbl({{ Rc = Ra & ~(mask( 8) << (Rb_or_imm<2:0> * 8)); }}); 219189SN/A 0x12: mskwl({{ Rc = Ra & ~(mask(16) << (Rb_or_imm<2:0> * 8)); }}); 220189SN/A 0x22: mskll({{ Rc = Ra & ~(mask(32) << (Rb_or_imm<2:0> * 8)); }}); 2212623SN/A 0x32: mskql({{ Rc = Ra & ~(mask(64) << (Rb_or_imm<2:0> * 8)); }}); 2222SN/A 223729SN/A 0x52: mskwh({{ 224334SN/A int bv = Rb_or_imm<2:0>; 2252SN/A Rc = bv ? (Ra & ~(mask(16) >> (64 - 8 * bv))) : Ra; 2262SN/A }}); 22711147Smitch.hayenga@arm.com 0x62: msklh({{ 22811147Smitch.hayenga@arm.com int bv = Rb_or_imm<2:0>; 2298834Satgutier@umich.edu Rc = bv ? (Ra & ~(mask(32) >> (64 - 8 * bv))) : Ra; 23011147Smitch.hayenga@arm.com }}); 23111147Smitch.hayenga@arm.com 0x72: mskqh({{ 23211147Smitch.hayenga@arm.com int bv = Rb_or_imm<2:0>; 2332SN/A Rc = bv ? (Ra & ~(mask(64) >> (64 - 8 * bv))) : Ra; 23411147Smitch.hayenga@arm.com }}); 23511147Smitch.hayenga@arm.com 23611147Smitch.hayenga@arm.com 0x06: extbl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }}); 23711147Smitch.hayenga@arm.com 0x16: extwl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<15:0>; }}); 2387897Shestness@cs.utexas.edu 0x26: extll({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<31:0>; }}); 23911147Smitch.hayenga@arm.com 0x36: extql({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8)); }}); 24011147Smitch.hayenga@arm.com 24111147Smitch.hayenga@arm.com 0x5a: extwh({{ 24211147Smitch.hayenga@arm.com Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<15:0>; }}); 2437897Shestness@cs.utexas.edu 0x6a: extlh({{ 24411147Smitch.hayenga@arm.com Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<31:0>; }}); 24511147Smitch.hayenga@arm.com 0x7a: extqh({{ 24611147Smitch.hayenga@arm.com Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>); }}); 24711147Smitch.hayenga@arm.com 2487897Shestness@cs.utexas.edu 0x0b: insbl({{ Rc = Ra< 7:0> << (Rb_or_imm<2:0> * 8); }}); 24911147Smitch.hayenga@arm.com 0x1b: inswl({{ Rc = Ra<15:0> << (Rb_or_imm<2:0> * 8); }}); 25011147Smitch.hayenga@arm.com 0x2b: insll({{ Rc = Ra<31:0> << (Rb_or_imm<2:0> * 8); }}); 25111147Smitch.hayenga@arm.com 0x3b: insql({{ Rc = Ra << (Rb_or_imm<2:0> * 8); }}); 25211147Smitch.hayenga@arm.com 2537897Shestness@cs.utexas.edu 0x57: inswh({{ 25411147Smitch.hayenga@arm.com int bv = Rb_or_imm<2:0>; 25511147Smitch.hayenga@arm.com Rc = bv ? (Ra.uq<15:0> >> (64 - 8 * bv)) : 0; 25611147Smitch.hayenga@arm.com }}); 25711147Smitch.hayenga@arm.com 0x67: inslh({{ 2587897Shestness@cs.utexas.edu int bv = Rb_or_imm<2:0>; 25911147Smitch.hayenga@arm.com Rc = bv ? (Ra.uq<31:0> >> (64 - 8 * bv)) : 0; 26011147Smitch.hayenga@arm.com }}); 26111147Smitch.hayenga@arm.com 0x77: insqh({{ 26211147Smitch.hayenga@arm.com int bv = Rb_or_imm<2:0>; 2637897Shestness@cs.utexas.edu Rc = bv ? (Ra.uq >> (64 - 8 * bv)) : 0; 26411147Smitch.hayenga@arm.com }}); 26511147Smitch.hayenga@arm.com 26611147Smitch.hayenga@arm.com 0x30: zap({{ 26711147Smitch.hayenga@arm.com uint64_t zapmask = 0; 2687897Shestness@cs.utexas.edu for (int i = 0; i < 8; ++i) { 26911147Smitch.hayenga@arm.com if (Rb_or_imm<i:>) 27011147Smitch.hayenga@arm.com zapmask |= (mask(8) << (i * 8)); 27111147Smitch.hayenga@arm.com } 27211147Smitch.hayenga@arm.com Rc = Ra & ~zapmask; 2737897Shestness@cs.utexas.edu }}); 27411147Smitch.hayenga@arm.com 0x31: zapnot({{ 27511147Smitch.hayenga@arm.com uint64_t zapmask = 0; 27611147Smitch.hayenga@arm.com for (int i = 0; i < 8; ++i) { 27711147Smitch.hayenga@arm.com if (!Rb_or_imm<i:>) 2787897Shestness@cs.utexas.edu zapmask |= (mask(8) << (i * 8)); 27911147Smitch.hayenga@arm.com } 28011147Smitch.hayenga@arm.com Rc = Ra & ~zapmask; 28111147Smitch.hayenga@arm.com }}); 28211147Smitch.hayenga@arm.com } 2837897Shestness@cs.utexas.edu 28411147Smitch.hayenga@arm.com 0x13: decode INTFUNC { // integer multiplies 28511147Smitch.hayenga@arm.com 0x00: mull({{ Rc.sl = Ra.sl * Rb_or_imm.sl; }}, IntMultOp); 28611147Smitch.hayenga@arm.com 0x20: mulq({{ Rc = Ra * Rb_or_imm; }}, IntMultOp); 28711147Smitch.hayenga@arm.com 0x30: umulh({{ 2889920Syasuko.eckert@amd.com uint64_t hi, lo; 28911147Smitch.hayenga@arm.com mul128(Ra, Rb_or_imm, hi, lo); 29011147Smitch.hayenga@arm.com Rc = hi; 29111147Smitch.hayenga@arm.com }}, IntMultOp); 29211147Smitch.hayenga@arm.com 0x40: mullv({{ 2939920Syasuko.eckert@amd.com // 32-bit multiply with trap on overflow 29411147Smitch.hayenga@arm.com int64_t Rax = Ra.sl; // sign extended version of Ra.sl 29511147Smitch.hayenga@arm.com int64_t Rbx = Rb_or_imm.sl; 29611147Smitch.hayenga@arm.com int64_t tmp = Rax * Rbx; 29711147Smitch.hayenga@arm.com // To avoid overflow, all the upper 32 bits must match 29811147Smitch.hayenga@arm.com // the sign bit of the lower 32. We code this as 2997897Shestness@cs.utexas.edu // checking the upper 33 bits for all 0s or all 1s. 30011147Smitch.hayenga@arm.com uint64_t sign_bits = tmp<63:31>; 30111147Smitch.hayenga@arm.com if (sign_bits != 0 && sign_bits != mask(33)) 30211147Smitch.hayenga@arm.com fault = new IntegerOverflowFault; 30311147Smitch.hayenga@arm.com Rc.sl = tmp<31:0>; 30411147Smitch.hayenga@arm.com }}, IntMultOp); 3057897Shestness@cs.utexas.edu 0x60: mulqv({{ 30611147Smitch.hayenga@arm.com // 64-bit multiply with trap on overflow 30711147Smitch.hayenga@arm.com uint64_t hi, lo; 30811147Smitch.hayenga@arm.com mul128(Ra, Rb_or_imm, hi, lo); 30911147Smitch.hayenga@arm.com // all the upper 64 bits must match the sign bit of 3102SN/A // the lower 64 31111147Smitch.hayenga@arm.com if (!((hi == 0 && lo<63:> == 0) || 31211147Smitch.hayenga@arm.com (hi == mask(64) && lo<63:> == 1))) 31311147Smitch.hayenga@arm.com fault = new IntegerOverflowFault; 31411147Smitch.hayenga@arm.com Rc = lo; 3151001SN/A }}, IntMultOp); 31611147Smitch.hayenga@arm.com } 31711147Smitch.hayenga@arm.com 31811147Smitch.hayenga@arm.com 0x1c: decode INTFUNC { 31911147Smitch.hayenga@arm.com 0x00: decode RA { 31: sextb({{ Rc.sb = Rb_or_imm< 7:0>; }}); } 3202SN/A 0x01: decode RA { 31: sextw({{ Rc.sw = Rb_or_imm<15:0>; }}); } 32111147Smitch.hayenga@arm.com 0x32: ctlz({{ 32211147Smitch.hayenga@arm.com uint64_t count = 0; 32311147Smitch.hayenga@arm.com uint64_t temp = Rb; 32411147Smitch.hayenga@arm.com if (temp<63:32>) temp >>= 32; else count += 32; 3257897Shestness@cs.utexas.edu if (temp<31:16>) temp >>= 16; else count += 16; 32611147Smitch.hayenga@arm.com if (temp<15:8>) temp >>= 8; else count += 8; 32711147Smitch.hayenga@arm.com if (temp<7:4>) temp >>= 4; else count += 4; 32811147Smitch.hayenga@arm.com if (temp<3:2>) temp >>= 2; else count += 2; 32911147Smitch.hayenga@arm.com if (temp<1:1>) temp >>= 1; else count += 1; 3307897Shestness@cs.utexas.edu if ((temp<0:0>) != 0x1) count += 1; 33111147Smitch.hayenga@arm.com Rc = count; 33211147Smitch.hayenga@arm.com }}, IntAluOp); 33311147Smitch.hayenga@arm.com 33411147Smitch.hayenga@arm.com 0x33: cttz({{ 3352SN/A uint64_t count = 0; 33611147Smitch.hayenga@arm.com uint64_t temp = Rb; 33711147Smitch.hayenga@arm.com if (!(temp<31:0>)) { temp >>= 32; count += 32; } 33811147Smitch.hayenga@arm.com if (!(temp<15:0>)) { temp >>= 16; count += 16; } 33911147Smitch.hayenga@arm.com if (!(temp<7:0>)) { temp >>= 8; count += 8; } 3402SN/A if (!(temp<3:0>)) { temp >>= 4; count += 4; } 34111147Smitch.hayenga@arm.com if (!(temp<1:0>)) { temp >>= 2; count += 2; } 34211147Smitch.hayenga@arm.com if (!(temp<0:0> & ULL(0x1))) count += 1; 34311147Smitch.hayenga@arm.com Rc = count; 34411147Smitch.hayenga@arm.com }}, IntAluOp); 34511147Smitch.hayenga@arm.com 34611147Smitch.hayenga@arm.com format FailUnimpl { 34711147Smitch.hayenga@arm.com 0x30: ctpop(); 34811147Smitch.hayenga@arm.com 0x31: perr(); 34911147Smitch.hayenga@arm.com 0x34: unpkbw(); 35011147Smitch.hayenga@arm.com 0x35: unpkbl(); 35111147Smitch.hayenga@arm.com 0x36: pkwb(); 35211147Smitch.hayenga@arm.com 0x37: pklb(); 35311147Smitch.hayenga@arm.com 0x38: minsb8(); 35411147Smitch.hayenga@arm.com 0x39: minsw4(); 35511147Smitch.hayenga@arm.com 0x3a: minub8(); 35611147Smitch.hayenga@arm.com 0x3b: minuw4(); 35711147Smitch.hayenga@arm.com 0x3c: maxub8(); 35811147Smitch.hayenga@arm.com 0x3d: maxuw4(); 35911147Smitch.hayenga@arm.com 0x3e: maxsb8(); 36011147Smitch.hayenga@arm.com 0x3f: maxsw4(); 36111147Smitch.hayenga@arm.com } 36211147Smitch.hayenga@arm.com 36311147Smitch.hayenga@arm.com format BasicOperateWithNopCheck { 36411147Smitch.hayenga@arm.com 0x70: decode RB { 36511147Smitch.hayenga@arm.com 31: ftoit({{ Rc = Fa.uq; }}, FloatCvtOp); 36611147Smitch.hayenga@arm.com } 36711147Smitch.hayenga@arm.com 0x78: decode RB { 36811147Smitch.hayenga@arm.com 31: ftois({{ Rc.sl = t_to_s(Fa.uq); }}, 36911147Smitch.hayenga@arm.com FloatCvtOp); 37011147Smitch.hayenga@arm.com } 37111147Smitch.hayenga@arm.com } 37211147Smitch.hayenga@arm.com } 37311147Smitch.hayenga@arm.com } 37411147Smitch.hayenga@arm.com 37511147Smitch.hayenga@arm.com // Conditional branches. 37611147Smitch.hayenga@arm.com format CondBranch { 37711147Smitch.hayenga@arm.com 0x39: beq({{ cond = (Ra == 0); }}); 37811147Smitch.hayenga@arm.com 0x3d: bne({{ cond = (Ra != 0); }}); 37911147Smitch.hayenga@arm.com 0x3e: bge({{ cond = (Ra.sq >= 0); }}); 38011147Smitch.hayenga@arm.com 0x3f: bgt({{ cond = (Ra.sq > 0); }}); 38111147Smitch.hayenga@arm.com 0x3b: ble({{ cond = (Ra.sq <= 0); }}); 38210193SCurtis.Dunham@arm.com 0x3a: blt({{ cond = (Ra.sq < 0); }}); 3832SN/A 0x38: blbc({{ cond = ((Ra & 1) == 0); }}); 3842SN/A 0x3c: blbs({{ cond = ((Ra & 1) == 1); }}); 3852SN/A 3862623SN/A 0x31: fbeq({{ cond = (Fa == 0); }}); 387334SN/A 0x35: fbne({{ cond = (Fa != 0); }}); 38811147Smitch.hayenga@arm.com 0x36: fbge({{ cond = (Fa >= 0); }}); 38911147Smitch.hayenga@arm.com 0x37: fbgt({{ cond = (Fa > 0); }}); 39011147Smitch.hayenga@arm.com 0x33: fble({{ cond = (Fa <= 0); }}); 391334SN/A 0x32: fblt({{ cond = (Fa < 0); }}); 392334SN/A } 393334SN/A 39410905Sandreas.sandberg@arm.com // unconditional branches 3952SN/A format UncondBranch { 3969448SAndreas.Sandberg@ARM.com 0x30: br(); 3979448SAndreas.Sandberg@ARM.com 0x34: bsr(IsCall); 39811147Smitch.hayenga@arm.com } 3992SN/A 4002SN/A // indirect branches 4012SN/A 0x1a: decode JMPFUNC { 40210905Sandreas.sandberg@arm.com format Jump { 4032SN/A 0: jmp(); 40411147Smitch.hayenga@arm.com 1: jsr(IsCall); 4052SN/A 2: ret(IsReturn); 4062SN/A 3: jsr_coroutine(IsCall, IsReturn); 4072SN/A } 4086221Snate@binkert.org } 4092SN/A 4102SN/A // Square root and integer-to-FP moves 4112SN/A 0x14: decode FP_SHORTFUNC { 4122SN/A // Integer to FP register moves must have RB == 31 4132623SN/A 0x4: decode RB { 4142SN/A 31: decode FP_FULLFUNC { 41511147Smitch.hayenga@arm.com format BasicOperateWithNopCheck { 4162SN/A 0x004: itofs({{ Fc.uq = s_to_t(Ra.ul); }}, FloatCvtOp); 4172SN/A 0x024: itoft({{ Fc.uq = Ra.uq; }}, FloatCvtOp); 4182SN/A 0x014: FailUnimpl::itoff(); // VAX-format conversion 41911151Smitch.hayenga@arm.com } 4202SN/A } 42111151Smitch.hayenga@arm.com } 42211151Smitch.hayenga@arm.com 42311151Smitch.hayenga@arm.com // Square root instructions must have FA == 31 42411151Smitch.hayenga@arm.com 0xb: decode FA { 42511151Smitch.hayenga@arm.com 31: decode FP_TYPEFUNC { 42611147Smitch.hayenga@arm.com format FloatingPointOperate { 4272SN/A#if SS_COMPATIBLE_FP 4282SN/A 0x0b: sqrts({{ 4292SN/A if (Fb < 0.0) 4302623SN/A fault = new ArithmeticFault; 4312SN/A Fc = sqrt(Fb); 43211147Smitch.hayenga@arm.com }}, FloatSqrtOp); 43311147Smitch.hayenga@arm.com#else 43411147Smitch.hayenga@arm.com 0x0b: sqrts({{ 43511147Smitch.hayenga@arm.com if (Fb.sf < 0.0) 4365704Snate@binkert.org fault = new ArithmeticFault; 43711150Smitch.hayenga@arm.com Fc.sf = sqrt(Fb.sf); 4382SN/A }}, FloatSqrtOp); 4393520Sgblack@eecs.umich.edu#endif 44011147Smitch.hayenga@arm.com 0x2b: sqrtt({{ 44111150Smitch.hayenga@arm.com if (Fb < 0.0) 4423520Sgblack@eecs.umich.edu fault = new ArithmeticFault; 4439023Sgblack@eecs.umich.edu Fc = sqrt(Fb); 4442SN/A }}, FloatSqrtOp); 4452SN/A } 4462623SN/A } 4472SN/A } 4482623SN/A 4495894Sgblack@eecs.umich.edu // VAX-format sqrtf and sqrtg are not implemented 4502662Sstever@eecs.umich.edu 0xa: FailUnimpl::sqrtfg(); 4512623SN/A } 45211147Smitch.hayenga@arm.com 45311147Smitch.hayenga@arm.com // IEEE floating point 45411147Smitch.hayenga@arm.com 0x16: decode FP_SHORTFUNC_TOP2 { 4557720Sgblack@eecs.umich.edu // The top two bits of the short function code break this 4564495Sacolyte@umich.edu // space into four groups: binary ops, compares, reserved, and 4572623SN/A // conversions. See Table 4-12 of AHB. There are different 4587720Sgblack@eecs.umich.edu // special cases in these different groups, so we decode on 4592623SN/A // these top two bits first just to select a decode strategy. 46011147Smitch.hayenga@arm.com // Most of these instructions may have various trapping and 4618832SAli.Saidi@ARM.com // rounding mode flags set; these are decoded in the 4628832SAli.Saidi@ARM.com // FloatingPointDecode template used by the 4632623SN/A // FloatingPointOperate format. 4642623SN/A 4652623SN/A // add/sub/mul/div: just decode on the short function code 4662623SN/A // and source type. All valid trapping and rounding modes apply. 4672623SN/A 0: decode FP_TRAPMODE { 4682623SN/A // check for valid trapping modes here 46911147Smitch.hayenga@arm.com 0,1,5,7: decode FP_TYPEFUNC { 47011147Smitch.hayenga@arm.com format FloatingPointOperate { 47111147Smitch.hayenga@arm.com#if SS_COMPATIBLE_FP 4722SN/A 0x00: adds({{ Fc = Fa + Fb; }}); 4732683Sktlim@umich.edu 0x01: subs({{ Fc = Fa - Fb; }}); 4742427SN/A 0x02: muls({{ Fc = Fa * Fb; }}, FloatMultOp); 4752683Sktlim@umich.edu 0x03: divs({{ Fc = Fa / Fb; }}, FloatDivOp); 4762427SN/A#else 4772SN/A 0x00: adds({{ Fc.sf = Fa.sf + Fb.sf; }}); 4782623SN/A 0x01: subs({{ Fc.sf = Fa.sf - Fb.sf; }}); 47911147Smitch.hayenga@arm.com 0x02: muls({{ Fc.sf = Fa.sf * Fb.sf; }}, FloatMultOp); 4807897Shestness@cs.utexas.edu 0x03: divs({{ Fc.sf = Fa.sf / Fb.sf; }}, FloatDivOp); 4812SN/A#endif 4822623SN/A 4832623SN/A 0x20: addt({{ Fc = Fa + Fb; }}); 4844377Sgblack@eecs.umich.edu 0x21: subt({{ Fc = Fa - Fb; }}); 4857720Sgblack@eecs.umich.edu 0x22: mult({{ Fc = Fa * Fb; }}, FloatMultOp); 4864377Sgblack@eecs.umich.edu 0x23: divt({{ Fc = Fa / Fb; }}, FloatDivOp); 4877720Sgblack@eecs.umich.edu } 48811147Smitch.hayenga@arm.com } 4897720Sgblack@eecs.umich.edu } 4907720Sgblack@eecs.umich.edu 4915665Sgblack@eecs.umich.edu // Floating-point compare instructions must have the default 4925665Sgblack@eecs.umich.edu // rounding mode, and may use the default trapping mode or 4934181Sgblack@eecs.umich.edu // /SU. Both trapping modes are treated the same by M5; the 4944181Sgblack@eecs.umich.edu // only difference on the real hardware (as far a I can tell) 4959023Sgblack@eecs.umich.edu // is that without /SU you'd get an imprecise trap if you 4969023Sgblack@eecs.umich.edu // tried to compare a NaN with something else (instead of an 4974181Sgblack@eecs.umich.edu // "unordered" result). 4984182Sgblack@eecs.umich.edu 1: decode FP_FULLFUNC { 49911147Smitch.hayenga@arm.com format BasicOperateWithNopCheck { 50011321Ssteve.reinhardt@amd.com 0x0a5, 0x5a5: cmpteq({{ Fc = (Fa == Fb) ? 2.0 : 0.0; }}, 5019023Sgblack@eecs.umich.edu FloatCmpOp); 5024593Sgblack@eecs.umich.edu 0x0a7, 0x5a7: cmptle({{ Fc = (Fa <= Fb) ? 2.0 : 0.0; }}, 5039023Sgblack@eecs.umich.edu FloatCmpOp); 5044377Sgblack@eecs.umich.edu 0x0a6, 0x5a6: cmptlt({{ Fc = (Fa < Fb) ? 2.0 : 0.0; }}, 5059023Sgblack@eecs.umich.edu FloatCmpOp); 5064377Sgblack@eecs.umich.edu 0x0a4, 0x5a4: cmptun({{ // unordered 5079023Sgblack@eecs.umich.edu Fc = (!(Fa < Fb) && !(Fa == Fb) && !(Fa > Fb)) ? 2.0 : 0.0; 5089023Sgblack@eecs.umich.edu }}, FloatCmpOp); 50911147Smitch.hayenga@arm.com } 5107720Sgblack@eecs.umich.edu } 5114377Sgblack@eecs.umich.edu 51211147Smitch.hayenga@arm.com // The FP-to-integer and integer-to-FP conversion insts 51311147Smitch.hayenga@arm.com // require that FA be 31. 5144377Sgblack@eecs.umich.edu 3: decode FA { 5154181Sgblack@eecs.umich.edu 31: decode FP_TYPEFUNC { 5164181Sgblack@eecs.umich.edu format FloatingPointOperate { 5174181Sgblack@eecs.umich.edu 0x2f: decode FP_ROUNDMODE { 5184539Sgblack@eecs.umich.edu format FPFixedRounding { 5193276Sgblack@eecs.umich.edu // "chopped" i.e. round toward zero 52011147Smitch.hayenga@arm.com 0: cvttq({{ Fc.sq = (int64_t)trunc(Fb); }}, 52111147Smitch.hayenga@arm.com Chopped); 5223280Sgblack@eecs.umich.edu // round to minus infinity 5233280Sgblack@eecs.umich.edu 1: cvttq({{ Fc.sq = (int64_t)floor(Fb); }}, 5243276Sgblack@eecs.umich.edu MinusInfinity); 5253276Sgblack@eecs.umich.edu } 5263276Sgblack@eecs.umich.edu default: cvttq({{ Fc.sq = (int64_t)nearbyint(Fb); }}); 5277720Sgblack@eecs.umich.edu } 5283276Sgblack@eecs.umich.edu 5293276Sgblack@eecs.umich.edu // The cvtts opcode is overloaded to be cvtst if the trap 5304181Sgblack@eecs.umich.edu // mode is 2 or 6 (which are not valid otherwise) 5318955Sgblack@eecs.umich.edu 0x2c: decode FP_FULLFUNC { 5324522Ssaidi@eecs.umich.edu format BasicOperateWithNopCheck { 53311147Smitch.hayenga@arm.com // trap on denorm version "cvtst/s" is 5347720Sgblack@eecs.umich.edu // simulated same as cvtst 5352470SN/A 0x2ac, 0x6ac: cvtst({{ Fc = Fb.sf; }}); 5368955Sgblack@eecs.umich.edu } 5374181Sgblack@eecs.umich.edu default: cvtts({{ Fc.sf = Fb; }}); 5384522Ssaidi@eecs.umich.edu } 5394181Sgblack@eecs.umich.edu 54010061Sandreas@sandberg.pp.se // The trapping mode for integer-to-FP conversions 54111147Smitch.hayenga@arm.com // must be /SUI or nothing; /U and /SU are not 54211147Smitch.hayenga@arm.com // allowed. The full set of rounding modes are 54310061Sandreas@sandberg.pp.se // supported though. 54410061Sandreas@sandberg.pp.se 0x3c: decode FP_TRAPMODE { 54510061Sandreas@sandberg.pp.se 0,7: cvtqs({{ Fc.sf = Fb.sq; }}); 54611147Smitch.hayenga@arm.com } 54710061Sandreas@sandberg.pp.se 0x3e: decode FP_TRAPMODE { 54811147Smitch.hayenga@arm.com 0,7: cvtqt({{ Fc = Fb.sq; }}); 54911147Smitch.hayenga@arm.com } 55010061Sandreas@sandberg.pp.se } 55110061Sandreas@sandberg.pp.se } 55211147Smitch.hayenga@arm.com } 55310061Sandreas@sandberg.pp.se } 5542623SN/A 5552623SN/A // misc FP operate 5562623SN/A 0x17: decode FP_FULLFUNC { 5572623SN/A format BasicOperateWithNopCheck { 5582623SN/A 0x010: cvtlq({{ 55911147Smitch.hayenga@arm.com Fc.sl = (Fb.uq<63:62> << 30) | Fb.uq<58:29>; 56011147Smitch.hayenga@arm.com }}); 56111147Smitch.hayenga@arm.com 0x030: cvtql({{ 5627720Sgblack@eecs.umich.edu Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29); 5637720Sgblack@eecs.umich.edu }}); 56411147Smitch.hayenga@arm.com 5657720Sgblack@eecs.umich.edu // We treat the precise & imprecise trapping versions of 5668780Sgblack@eecs.umich.edu // cvtql identically. 56711147Smitch.hayenga@arm.com 0x130, 0x530: cvtqlv({{ 5687720Sgblack@eecs.umich.edu // To avoid overflow, all the upper 32 bits must match 56911147Smitch.hayenga@arm.com // the sign bit of the lower 32. We code this as 57011147Smitch.hayenga@arm.com // checking the upper 33 bits for all 0s or all 1s. 5712623SN/A uint64_t sign_bits = Fb.uq<63:31>; 5722683Sktlim@umich.edu if (sign_bits != 0 && sign_bits != mask(33)) 5732623SN/A fault = new IntegerOverflowFault; 5742SN/A Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29); 5752623SN/A }}); 57611147Smitch.hayenga@arm.com 5772SN/A 0x020: cpys({{ // copy sign 5782SN/A Fc.uq = (Fa.uq<63:> << 63) | Fb.uq<62:0>; 5792623SN/A }}); 58011147Smitch.hayenga@arm.com 0x021: cpysn({{ // copy sign negated 58111147Smitch.hayenga@arm.com Fc.uq = (~Fa.uq<63:> << 63) | Fb.uq<62:0>; 5822623SN/A }}); 5832SN/A 0x022: cpyse({{ // copy sign and exponent 5845953Ssaidi@eecs.umich.edu Fc.uq = (Fa.uq<63:52> << 52) | Fb.uq<51:0>; 58511147Smitch.hayenga@arm.com }}); 5865953Ssaidi@eecs.umich.edu 5875953Ssaidi@eecs.umich.edu 0x02a: fcmoveq({{ Fc = (Fa == 0) ? Fb : Fc; }}); 58810061Sandreas@sandberg.pp.se 0x02b: fcmovne({{ Fc = (Fa != 0) ? Fb : Fc; }}); 58911147Smitch.hayenga@arm.com 0x02c: fcmovlt({{ Fc = (Fa < 0) ? Fb : Fc; }}); 59010061Sandreas@sandberg.pp.se 0x02d: fcmovge({{ Fc = (Fa >= 0) ? Fb : Fc; }}); 59110061Sandreas@sandberg.pp.se 0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }}); 5927897Shestness@cs.utexas.edu 0x02f: fcmovgt({{ Fc = (Fa > 0) ? Fb : Fc; }}); 5937897Shestness@cs.utexas.edu 5947897Shestness@cs.utexas.edu 0x024: mt_fpcr({{ FPCR = Fa.uq; }}); 59511147Smitch.hayenga@arm.com 0x025: mf_fpcr({{ Fa.uq = FPCR; }}); 59611147Smitch.hayenga@arm.com } 5977897Shestness@cs.utexas.edu } 5987897Shestness@cs.utexas.edu 5997897Shestness@cs.utexas.edu // miscellaneous mem-format ops 6007897Shestness@cs.utexas.edu 0x18: decode MEMFUNC { 60111147Smitch.hayenga@arm.com format WarnUnimpl { 60211147Smitch.hayenga@arm.com 0x8000: fetch(); 6037897Shestness@cs.utexas.edu 0xa000: fetch_m(); 60411147Smitch.hayenga@arm.com 0xe800: ecb(); 6057897Shestness@cs.utexas.edu } 6067897Shestness@cs.utexas.edu 60711147Smitch.hayenga@arm.com format MiscPrefetch { 6087897Shestness@cs.utexas.edu 0xf800: wh64({{ EA = Rb & ~ULL(63); }}, 60911147Smitch.hayenga@arm.com {{ xc->writeHint(EA, 64, memAccessFlags); }}, 6107897Shestness@cs.utexas.edu mem_flags = NO_FAULT, 6117897Shestness@cs.utexas.edu inst_flags = [IsMemRef, IsDataPrefetch, 61211147Smitch.hayenga@arm.com IsStore, MemWriteOp]); 6137897Shestness@cs.utexas.edu } 61411147Smitch.hayenga@arm.com 6157897Shestness@cs.utexas.edu format BasicOperate { 6167897Shestness@cs.utexas.edu 0xc000: rpcc({{ 61711147Smitch.hayenga@arm.com#if FULL_SYSTEM 6187897Shestness@cs.utexas.edu /* Rb is a fake dependency so here is a fun way to get 61911147Smitch.hayenga@arm.com * the parser to understand that. 6207897Shestness@cs.utexas.edu */ 62111147Smitch.hayenga@arm.com Ra = xc->readMiscRegWithEffect(AlphaISA::IPR_CC, fault) + (Rb & 0); 6227897Shestness@cs.utexas.edu 6237897Shestness@cs.utexas.edu#else 6247897Shestness@cs.utexas.edu Ra = curTick; 62511147Smitch.hayenga@arm.com#endif 62610193SCurtis.Dunham@arm.com }}); 6278780Sgblack@eecs.umich.edu 6288780Sgblack@eecs.umich.edu // All of the barrier instructions below do nothing in 6292644Sstever@eecs.umich.edu // their execute() methods (hence the empty code blocks). 6302644Sstever@eecs.umich.edu // All of their functionality is hard-coded in the 6314046Sbinkertn@umich.edu // pipeline based on the flags IsSerializing, 6324046Sbinkertn@umich.edu // IsMemBarrier, and IsWriteBarrier. In the current 6334046Sbinkertn@umich.edu // detailed CPU model, the execute() function only gets 6342644Sstever@eecs.umich.edu // called at fetch, so there's no way to generate pipeline 63510464SAndreas.Sandberg@ARM.com // behavior at any other stage. Once we go to an 63610464SAndreas.Sandberg@ARM.com // exec-in-exec CPU model we should be able to get rid of 63710464SAndreas.Sandberg@ARM.com // these flags and implement this behavior via the 6382623SN/A // execute() methods. 6392SN/A 6402623SN/A // trapb is just a barrier on integer traps, where excb is 64110379Sandreas.hansson@arm.com // a barrier on integer and FP traps. "EXCB is thus a 6422623SN/A // superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat 64311147Smitch.hayenga@arm.com // them the same though. 64411147Smitch.hayenga@arm.com 0x0000: trapb({{ }}, IsSerializing, No_OpClass); 64511147Smitch.hayenga@arm.com 0x0400: excb({{ }}, IsSerializing, No_OpClass); 64610061Sandreas@sandberg.pp.se 0x4000: mb({{ }}, IsMemBarrier, MemReadOp); 64710061Sandreas@sandberg.pp.se 0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp); 6484377Sgblack@eecs.umich.edu } 64911147Smitch.hayenga@arm.com 6502090SN/A#if FULL_SYSTEM 6513905Ssaidi@eecs.umich.edu format BasicOperate { 65211147Smitch.hayenga@arm.com 0xe000: rc({{ 6539023Sgblack@eecs.umich.edu Ra = xc->readIntrFlag(); 6544377Sgblack@eecs.umich.edu xc->setIntrFlag(0); 6557720Sgblack@eecs.umich.edu }}, IsNonSpeculative); 6567720Sgblack@eecs.umich.edu 0xf000: rs({{ 6577720Sgblack@eecs.umich.edu Ra = xc->readIntrFlag(); 6587720Sgblack@eecs.umich.edu xc->setIntrFlag(1); 6597720Sgblack@eecs.umich.edu }}, IsNonSpeculative); 6607720Sgblack@eecs.umich.edu } 6613276Sgblack@eecs.umich.edu#else 6622SN/A format FailUnimpl { 66310061Sandreas@sandberg.pp.se 0xe000: rc(); 66410061Sandreas@sandberg.pp.se 0xf000: rs(); 66510061Sandreas@sandberg.pp.se } 66610061Sandreas@sandberg.pp.se#endif 66710061Sandreas@sandberg.pp.se } 66810061Sandreas@sandberg.pp.se 66911147Smitch.hayenga@arm.com#if FULL_SYSTEM 67010061Sandreas@sandberg.pp.se 0x00: CallPal::call_pal({{ 67111147Smitch.hayenga@arm.com if (!palValid || 67210061Sandreas@sandberg.pp.se (palPriv 67310061Sandreas@sandberg.pp.se && xc->readMiscRegWithEffect(AlphaISA::IPR_ICM, fault) != AlphaISA::mode_kernel)) { 67411147Smitch.hayenga@arm.com // invalid pal function code, or attempt to do privileged 67511147Smitch.hayenga@arm.com // PAL call in non-kernel mode 67610061Sandreas@sandberg.pp.se fault = new UnimplementedOpcodeFault; 67710061Sandreas@sandberg.pp.se } 6782SN/A else { 6792SN/A // check to see if simulator wants to do something special 6809461Snilay@cs.wisc.edu // on this PAL call (including maybe suppress it) 6819461Snilay@cs.wisc.edu bool dopal = xc->simPalCheck(palFunc); 6829461Snilay@cs.wisc.edu 6839461Snilay@cs.wisc.edu if (dopal) { 68411147Smitch.hayenga@arm.com xc->setMiscRegWithEffect(AlphaISA::IPR_EXC_ADDR, NPC); 68511147Smitch.hayenga@arm.com NPC = xc->readMiscRegWithEffect(AlphaISA::IPR_PAL_BASE, fault) + palOffset; 6869461Snilay@cs.wisc.edu } 687 } 688 }}, IsNonSpeculative); 689#else 690 0x00: decode PALFUNC { 691 format EmulatedCallPal { 692 0x00: halt ({{ 693 SimExit(curTick, "halt instruction encountered"); 694 }}, IsNonSpeculative); 695 0x83: callsys({{ 696 xc->syscall(); 697 }}, IsNonSpeculative); 698 // Read uniq reg into ABI return value register (r0) 699 0x9e: rduniq({{ R0 = Runiq; }}); 700 // Write uniq reg with value from ABI arg register (r16) 701 0x9f: wruniq({{ Runiq = R16; }}); 702 } 703 } 704#endif 705 706#if FULL_SYSTEM 707 0x1b: decode PALMODE { 708 0: OpcdecFault::hw_st_quad(); 709 1: decode HW_LDST_QUAD { 710 format HwLoad { 711 0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }}, L); 712 1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }}, Q); 713 } 714 } 715 } 716 717 0x1f: decode PALMODE { 718 0: OpcdecFault::hw_st_cond(); 719 format HwStore { 720 1: decode HW_LDST_COND { 721 0: decode HW_LDST_QUAD { 722 0: hw_st({{ EA = (Rb + disp) & ~3; }}, 723 {{ Mem.ul = Ra<31:0>; }}, L); 724 1: hw_st({{ EA = (Rb + disp) & ~7; }}, 725 {{ Mem.uq = Ra.uq; }}, Q); 726 } 727 728 1: FailUnimpl::hw_st_cond(); 729 } 730 } 731 } 732 733 0x19: decode PALMODE { 734 0: OpcdecFault::hw_mfpr(); 735 format HwMoveIPR { 736 1: hw_mfpr({{ 737 Ra = xc->readMiscRegWithEffect(ipr_index, fault); 738 }}); 739 } 740 } 741 742 0x1d: decode PALMODE { 743 0: OpcdecFault::hw_mtpr(); 744 format HwMoveIPR { 745 1: hw_mtpr({{ 746 xc->setMiscRegWithEffect(ipr_index, Ra); 747 if (traceData) { traceData->setData(Ra); } 748 }}); 749 } 750 } 751 752 format BasicOperate { 753 0x1e: decode PALMODE { 754 0: OpcdecFault::hw_rei(); 755 1:hw_rei({{ xc->hwrei(); }}, IsSerializing); 756 } 757 758 // M5 special opcodes use the reserved 0x01 opcode space 759 0x01: decode M5FUNC { 760 0x00: arm({{ 761 AlphaPseudo::arm(xc->xcBase()); 762 }}, IsNonSpeculative); 763 0x01: quiesce({{ 764 AlphaPseudo::quiesce(xc->xcBase()); 765 }}, IsNonSpeculative); 766 0x02: quiesceNs({{ 767 AlphaPseudo::quiesceNs(xc->xcBase(), R16); 768 }}, IsNonSpeculative); 769 0x03: quiesceCycles({{ 770 AlphaPseudo::quiesceCycles(xc->xcBase(), R16); 771 }}, IsNonSpeculative); 772 0x04: quiesceTime({{ 773 R0 = AlphaPseudo::quiesceTime(xc->xcBase()); 774 }}, IsNonSpeculative); 775 0x10: ivlb({{ 776 AlphaPseudo::ivlb(xc->xcBase()); 777 }}, No_OpClass, IsNonSpeculative); 778 0x11: ivle({{ 779 AlphaPseudo::ivle(xc->xcBase()); 780 }}, No_OpClass, IsNonSpeculative); 781 0x20: m5exit_old({{ 782 AlphaPseudo::m5exit_old(xc->xcBase()); 783 }}, No_OpClass, IsNonSpeculative); 784 0x21: m5exit({{ 785 AlphaPseudo::m5exit(xc->xcBase(), R16); 786 }}, No_OpClass, IsNonSpeculative); 787 0x30: initparam({{ Ra = xc->xcBase()->getCpuPtr()->system->init_param; }}); 788 0x40: resetstats({{ 789 AlphaPseudo::resetstats(xc->xcBase(), R16, R17); 790 }}, IsNonSpeculative); 791 0x41: dumpstats({{ 792 AlphaPseudo::dumpstats(xc->xcBase(), R16, R17); 793 }}, IsNonSpeculative); 794 0x42: dumpresetstats({{ 795 AlphaPseudo::dumpresetstats(xc->xcBase(), R16, R17); 796 }}, IsNonSpeculative); 797 0x43: m5checkpoint({{ 798 AlphaPseudo::m5checkpoint(xc->xcBase(), R16, R17); 799 }}, IsNonSpeculative); 800 0x50: m5readfile({{ 801 R0 = AlphaPseudo::readfile(xc->xcBase(), R16, R17, R18); 802 }}, IsNonSpeculative); 803 0x51: m5break({{ 804 AlphaPseudo::debugbreak(xc->xcBase()); 805 }}, IsNonSpeculative); 806 0x52: m5switchcpu({{ 807 AlphaPseudo::switchcpu(xc->xcBase()); 808 }}, IsNonSpeculative); 809 0x53: m5addsymbol({{ 810 AlphaPseudo::addsymbol(xc->xcBase(), R16, R17); 811 }}, IsNonSpeculative); 812 0x54: m5panic({{ 813 panic("M5 panic instruction called at pc=%#x.", xc->readPC()); 814 }}, IsNonSpeculative); 815 816 } 817 } 818#endif 819} 820