ev5.hh revision 5568:d14250d688d2
15659Sgblack@eecs.umich.edu/* 25659Sgblack@eecs.umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 35659Sgblack@eecs.umich.edu * All rights reserved. 45659Sgblack@eecs.umich.edu * 55659Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 65659Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 75659Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 85659Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 95659Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 105659Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 115659Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 125659Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 135659Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 145659Sgblack@eecs.umich.edu * this software without specific prior written permission. 155659Sgblack@eecs.umich.edu * 165659Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175659Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185659Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195659Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205659Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215659Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225659Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235659Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245659Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255659Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265659Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275659Sgblack@eecs.umich.edu * 285659Sgblack@eecs.umich.edu * Authors: Steve Reinhardt 295659Sgblack@eecs.umich.edu * Nathan Binkert 305659Sgblack@eecs.umich.edu * Ali Saidi 315659Sgblack@eecs.umich.edu */ 325659Sgblack@eecs.umich.edu 335659Sgblack@eecs.umich.edu#ifndef __ARCH_ALPHA_EV5_HH__ 346215Snate@binkert.org#define __ARCH_ALPHA_EV5_HH__ 355659Sgblack@eecs.umich.edu 365659Sgblack@eecs.umich.edu#include "config/alpha_tlaser.hh" 375659Sgblack@eecs.umich.edu#include "arch/alpha/isa_traits.hh" 385659Sgblack@eecs.umich.edu 395659Sgblack@eecs.umich.edunamespace AlphaISA { 405659Sgblack@eecs.umich.edu 415659Sgblack@eecs.umich.edu#if ALPHA_TLASER 425659Sgblack@eecs.umich.educonst uint64_t AsnMask = ULL(0x7f); 435659Sgblack@eecs.umich.edu#else 445659Sgblack@eecs.umich.educonst uint64_t AsnMask = ULL(0xff); 455659Sgblack@eecs.umich.edu#endif 465659Sgblack@eecs.umich.edu 475659Sgblack@eecs.umich.educonst int VAddrImplBits = 43; 485659Sgblack@eecs.umich.educonst Addr VAddrImplMask = (ULL(1) << VAddrImplBits) - 1; 495659Sgblack@eecs.umich.educonst Addr VAddrUnImplMask = ~VAddrImplMask; 505659Sgblack@eecs.umich.eduinline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; } 515659Sgblack@eecs.umich.eduinline Addr VAddrVPN(Addr a) { return a >> PageShift; } 525659Sgblack@eecs.umich.eduinline Addr VAddrOffset(Addr a) { return a & PageOffset; } 535659Sgblack@eecs.umich.eduinline Addr VAddrSpaceEV5(Addr a) { return a >> 41 & 0x3; } 545659Sgblack@eecs.umich.eduinline Addr VAddrSpaceEV6(Addr a) { return a >> 41 & 0x7f; } 555659Sgblack@eecs.umich.edu 565659Sgblack@eecs.umich.edu#if ALPHA_TLASER 575659Sgblack@eecs.umich.eduinline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFF00000); } 585659Sgblack@eecs.umich.educonst int PAddrImplBits = 40; 595659Sgblack@eecs.umich.edu#else 605659Sgblack@eecs.umich.eduinline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFFF00000); } 615659Sgblack@eecs.umich.educonst int PAddrImplBits = 44; // for Tsunami 62#endif 63const Addr PAddrImplMask = (ULL(1) << PAddrImplBits) - 1; 64const Addr PAddrUncachedBit39 = ULL(0x8000000000); 65const Addr PAddrUncachedBit40 = ULL(0x10000000000); 66const Addr PAddrUncachedBit43 = ULL(0x80000000000); 67const Addr PAddrUncachedMask = ULL(0x807ffffffff); // Clear PA<42:35> 68inline Addr Phys2K0Seg(Addr addr) 69{ 70#if !ALPHA_TLASER 71 if (addr & PAddrUncachedBit43) { 72 addr &= PAddrUncachedMask; 73 addr |= PAddrUncachedBit40; 74 } 75#endif 76 return addr | K0SegBase; 77} 78 79inline int DTB_ASN_ASN(uint64_t reg) { return reg >> 57 & AsnMask; } 80inline Addr DTB_PTE_PPN(uint64_t reg) 81{ return reg >> 32 & (ULL(1) << PAddrImplBits - PageShift) - 1; } 82inline int DTB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; } 83inline int DTB_PTE_XWE(uint64_t reg) { return reg >> 12 & 0xf; } 84inline int DTB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; } 85inline int DTB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; } 86inline int DTB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; } 87inline int DTB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; } 88 89inline int ITB_ASN_ASN(uint64_t reg) { return reg >> 4 & AsnMask; } 90inline Addr ITB_PTE_PPN(uint64_t reg) 91{ return reg >> 32 & (ULL(1) << PAddrImplBits - PageShift) - 1; } 92inline int ITB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; } 93inline bool ITB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; } 94inline bool ITB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; } 95inline int ITB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; } 96inline bool ITB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; } 97 98inline uint64_t MCSR_SP(uint64_t reg) { return reg >> 1 & 0x3; } 99 100inline bool ICSR_SDE(uint64_t reg) { return reg >> 30 & 0x1; } 101inline int ICSR_SPE(uint64_t reg) { return reg >> 28 & 0x3; } 102inline bool ICSR_FPE(uint64_t reg) { return reg >> 26 & 0x1; } 103 104inline uint64_t ALT_MODE_AM(uint64_t reg) { return reg >> 3 & 0x3; } 105inline uint64_t DTB_CM_CM(uint64_t reg) { return reg >> 3 & 0x3; } 106inline uint64_t ICM_CM(uint64_t reg) { return reg >> 3 & 0x3; } 107 108const uint64_t MM_STAT_BAD_VA_MASK = ULL(0x0020); 109const uint64_t MM_STAT_DTB_MISS_MASK = ULL(0x0010); 110const uint64_t MM_STAT_FONW_MASK = ULL(0x0008); 111const uint64_t MM_STAT_FONR_MASK = ULL(0x0004); 112const uint64_t MM_STAT_ACV_MASK = ULL(0x0002); 113const uint64_t MM_STAT_WR_MASK = ULL(0x0001); 114inline int Opcode(MachInst inst) { return inst >> 26 & 0x3f; } 115inline int Ra(MachInst inst) { return inst >> 21 & 0x1f; } 116 117const Addr PalBase = 0x4000; 118const Addr PalMax = 0x10000; 119 120} // namespace AlphaISA 121 122#endif // __ARCH_ALPHA_EV5_HH__ 123