ev5.hh revision 2632:1bb2f91485ea
1955SN/A/* 2955SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 31762SN/A * All rights reserved. 4955SN/A * 5955SN/A * Redistribution and use in source and binary forms, with or without 6955SN/A * modification, are permitted provided that the following conditions are 7955SN/A * met: redistributions of source code must retain the above copyright 8955SN/A * notice, this list of conditions and the following disclaimer; 9955SN/A * redistributions in binary form must reproduce the above copyright 10955SN/A * notice, this list of conditions and the following disclaimer in the 11955SN/A * documentation and/or other materials provided with the distribution; 12955SN/A * neither the name of the copyright holders nor the names of its 13955SN/A * contributors may be used to endorse or promote products derived from 14955SN/A * this software without specific prior written permission. 15955SN/A * 16955SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17955SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18955SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19955SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20955SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21955SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22955SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23955SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24955SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25955SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26955SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27955SN/A */ 282665Ssaidi@eecs.umich.edu 292665Ssaidi@eecs.umich.edu#ifndef __ARCH_ALPHA_EV5_HH__ 30955SN/A#define __ARCH_ALPHA_EV5_HH__ 31955SN/A 32955SN/A#include "config/alpha_tlaser.hh" 33955SN/A#include "arch/alpha/isa_traits.hh" 34955SN/A 352632Sstever@eecs.umich.edunamespace EV5 { 362632Sstever@eecs.umich.edu 372632Sstever@eecs.umich.edu//It seems like a safe assumption EV5 only applies to alpha 382632Sstever@eecs.umich.eduusing namespace AlphaISA; 39955SN/A 402632Sstever@eecs.umich.edu#if ALPHA_TLASER 412632Sstever@eecs.umich.educonst uint64_t AsnMask = ULL(0x7f); 422761Sstever@eecs.umich.edu#else 432632Sstever@eecs.umich.educonst uint64_t AsnMask = ULL(0xff); 442632Sstever@eecs.umich.edu#endif 452632Sstever@eecs.umich.edu 462761Sstever@eecs.umich.educonst int VAddrImplBits = 43; 472761Sstever@eecs.umich.educonst Addr VAddrImplMask = (ULL(1) << VAddrImplBits) - 1; 482761Sstever@eecs.umich.educonst Addr VAddrUnImplMask = ~VAddrImplMask; 492632Sstever@eecs.umich.eduinline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; } 502632Sstever@eecs.umich.eduinline Addr VAddrVPN(Addr a) { return a >> AlphaISA::PageShift; } 512761Sstever@eecs.umich.eduinline Addr VAddrOffset(Addr a) { return a & AlphaISA::PageOffset; } 522761Sstever@eecs.umich.eduinline Addr VAddrSpaceEV5(Addr a) { return a >> 41 & 0x3; } 532761Sstever@eecs.umich.eduinline Addr VAddrSpaceEV6(Addr a) { return a >> 41 & 0x7f; } 542761Sstever@eecs.umich.edu 552761Sstever@eecs.umich.edu#if ALPHA_TLASER 562632Sstever@eecs.umich.eduinline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFF00000); } 572632Sstever@eecs.umich.educonst int PAddrImplBits = 40; 582632Sstever@eecs.umich.edu#else 592632Sstever@eecs.umich.eduinline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFFF00000); } 602632Sstever@eecs.umich.educonst int PAddrImplBits = 44; // for Tsunami 612632Sstever@eecs.umich.edu#endif 622632Sstever@eecs.umich.educonst Addr PAddrImplMask = (ULL(1) << PAddrImplBits) - 1; 63955SN/Aconst Addr PAddrUncachedBit39 = ULL(0x8000000000); 64955SN/Aconst Addr PAddrUncachedBit40 = ULL(0x10000000000); 65955SN/Aconst Addr PAddrUncachedBit43 = ULL(0x80000000000); 66955SN/Aconst Addr PAddrUncachedMask = ULL(0x807ffffffff); // Clear PA<42:35> 67955SN/Ainline Addr Phys2K0Seg(Addr addr) 685396Ssaidi@eecs.umich.edu{ 694202Sbinkertn@umich.edu#if !ALPHA_TLASER 705342Sstever@gmail.com if (addr & PAddrUncachedBit43) { 71955SN/A addr &= PAddrUncachedMask; 725273Sstever@gmail.com addr |= PAddrUncachedBit40; 735273Sstever@gmail.com } 742656Sstever@eecs.umich.edu#endif 752656Sstever@eecs.umich.edu return addr | AlphaISA::K0SegBase; 762656Sstever@eecs.umich.edu} 772656Sstever@eecs.umich.edu 782656Sstever@eecs.umich.eduinline int DTB_ASN_ASN(uint64_t reg) { return reg >> 57 & AsnMask; } 792656Sstever@eecs.umich.eduinline Addr DTB_PTE_PPN(uint64_t reg) 802656Sstever@eecs.umich.edu{ return reg >> 32 & (ULL(1) << PAddrImplBits - AlphaISA::PageShift) - 1; } 812653Sstever@eecs.umich.eduinline int DTB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; } 825227Ssaidi@eecs.umich.eduinline int DTB_PTE_XWE(uint64_t reg) { return reg >> 12 & 0xf; } 835227Ssaidi@eecs.umich.eduinline int DTB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; } 845227Ssaidi@eecs.umich.eduinline int DTB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; } 855227Ssaidi@eecs.umich.eduinline int DTB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; } 865396Ssaidi@eecs.umich.eduinline int DTB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; } 875396Ssaidi@eecs.umich.edu 885396Ssaidi@eecs.umich.eduinline int ITB_ASN_ASN(uint64_t reg) { return reg >> 4 & AsnMask; } 895396Ssaidi@eecs.umich.eduinline Addr ITB_PTE_PPN(uint64_t reg) 905396Ssaidi@eecs.umich.edu{ return reg >> 32 & (ULL(1) << PAddrImplBits - AlphaISA::PageShift) - 1; } 915396Ssaidi@eecs.umich.eduinline int ITB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; } 925396Ssaidi@eecs.umich.eduinline bool ITB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; } 935396Ssaidi@eecs.umich.eduinline bool ITB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; } 945588Ssaidi@eecs.umich.eduinline int ITB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; } 955396Ssaidi@eecs.umich.eduinline bool ITB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; } 965396Ssaidi@eecs.umich.edu 975396Ssaidi@eecs.umich.eduinline uint64_t MCSR_SP(uint64_t reg) { return reg >> 1 & 0x3; } 985396Ssaidi@eecs.umich.edu 995396Ssaidi@eecs.umich.eduinline bool ICSR_SDE(uint64_t reg) { return reg >> 30 & 0x1; } 1005396Ssaidi@eecs.umich.eduinline int ICSR_SPE(uint64_t reg) { return reg >> 28 & 0x3; } 1015396Ssaidi@eecs.umich.eduinline bool ICSR_FPE(uint64_t reg) { return reg >> 26 & 0x1; } 1025396Ssaidi@eecs.umich.edu 1035396Ssaidi@eecs.umich.eduinline uint64_t ALT_MODE_AM(uint64_t reg) { return reg >> 3 & 0x3; } 1045396Ssaidi@eecs.umich.eduinline uint64_t DTB_CM_CM(uint64_t reg) { return reg >> 3 & 0x3; } 1055396Ssaidi@eecs.umich.eduinline uint64_t ICM_CM(uint64_t reg) { return reg >> 3 & 0x3; } 1065396Ssaidi@eecs.umich.edu 1075396Ssaidi@eecs.umich.educonst uint64_t MM_STAT_BAD_VA_MASK = ULL(0x0020); 1085396Ssaidi@eecs.umich.educonst uint64_t MM_STAT_DTB_MISS_MASK = ULL(0x0010); 1095396Ssaidi@eecs.umich.educonst uint64_t MM_STAT_FONW_MASK = ULL(0x0008); 1105396Ssaidi@eecs.umich.educonst uint64_t MM_STAT_FONR_MASK = ULL(0x0004); 1115396Ssaidi@eecs.umich.educonst uint64_t MM_STAT_ACV_MASK = ULL(0x0002); 1125396Ssaidi@eecs.umich.educonst uint64_t MM_STAT_WR_MASK = ULL(0x0001); 1135396Ssaidi@eecs.umich.eduinline int Opcode(AlphaISA::MachInst inst) { return inst >> 26 & 0x3f; } 1145396Ssaidi@eecs.umich.eduinline int Ra(AlphaISA::MachInst inst) { return inst >> 21 & 0x1f; } 1155396Ssaidi@eecs.umich.edu 1165396Ssaidi@eecs.umich.educonst Addr PalBase = 0x4000; 1175396Ssaidi@eecs.umich.educonst Addr PalMax = 0x10000; 1185396Ssaidi@eecs.umich.edu 1195396Ssaidi@eecs.umich.edu/* namespace EV5 */ } 1205396Ssaidi@eecs.umich.edu 1215396Ssaidi@eecs.umich.edu#endif // __ARCH_ALPHA_EV5_HH__ 1225396Ssaidi@eecs.umich.edu