ev5.hh revision 1805
16019Shines@cs.fsu.edu/* 212110SRekai.GonzalezAlberquilla@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 37091Sgblack@eecs.umich.edu * All rights reserved. 47091Sgblack@eecs.umich.edu * 57091Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 67091Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 77091Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 87091Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 97091Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 107091Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 117091Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 127091Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 137091Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 146019Shines@cs.fsu.edu * this software without specific prior written permission. 156019Shines@cs.fsu.edu * 166019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276019Shines@cs.fsu.edu */ 286019Shines@cs.fsu.edu 296019Shines@cs.fsu.edu#ifndef __ARCH_ALPHA_EV5_HH__ 306019Shines@cs.fsu.edu#define __ARCH_ALPHA_EV5_HH__ 316019Shines@cs.fsu.edu 326019Shines@cs.fsu.edunamespace EV5 { 336019Shines@cs.fsu.edu 346019Shines@cs.fsu.edu#ifdef ALPHA_TLASER 356019Shines@cs.fsu.educonst uint64_t AsnMask = ULL(0x7f); 366019Shines@cs.fsu.edu#else 376019Shines@cs.fsu.educonst uint64_t AsnMask = ULL(0xff); 386019Shines@cs.fsu.edu#endif 396019Shines@cs.fsu.edu 406019Shines@cs.fsu.educonst int VAddrImplBits = 43; 416019Shines@cs.fsu.educonst Addr VAddrImplMask = (ULL(1) << VAddrImplBits) - 1; 426019Shines@cs.fsu.educonst Addr VAddrUnImplMask = ~VAddrImplMask; 438449Sgblack@eecs.umich.eduinline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; } 448449Sgblack@eecs.umich.eduinline Addr VAddrVPN(Addr a) { return a >> AlphaISA::PageShift; } 458449Sgblack@eecs.umich.eduinline Addr VAddrOffset(Addr a) { return a & AlphaISA::PageOffset; } 468449Sgblack@eecs.umich.eduinline Addr VAddrSpaceEV5(Addr a) { return a >> 41 & 0x3; } 478449Sgblack@eecs.umich.eduinline Addr VAddrSpaceEV6(Addr a) { return a >> 41 & 0x7f; } 488449Sgblack@eecs.umich.edu 4913759Sgiacomo.gabrielli@arm.com#ifdef ALPHA_TLASER 508449Sgblack@eecs.umich.eduinline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFF00000); } 5112386Sgabeblack@google.comconst int PAddrImplBits = 40; 528449Sgblack@eecs.umich.edu#else 5312110SRekai.GonzalezAlberquilla@arm.cominline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFFF00000); } 5413915Sgabeblack@google.comconst int PAddrImplBits = 44; // for Tsunami 5512110SRekai.GonzalezAlberquilla@arm.com#endif 5612110SRekai.GonzalezAlberquilla@arm.comconst Addr PAddrImplMask = (ULL(1) << PAddrImplBits) - 1; 5713759Sgiacomo.gabrielli@arm.comconst Addr PAddrUncachedBit39 = ULL(0x8000000000); 5813759Sgiacomo.gabrielli@arm.comconst Addr PAddrUncachedBit40 = ULL(0x10000000000); 5913915Sgabeblack@google.comconst Addr PAddrUncachedBit43 = ULL(0x80000000000); 6013759Sgiacomo.gabrielli@arm.comconst Addr PAddrUncachedMask = ULL(0x807ffffffff); // Clear PA<42:35> 616019Shines@cs.fsu.eduinline Addr Phys2K0Seg(Addr addr) 626019Shines@cs.fsu.edu{ 636312Sgblack@eecs.umich.edu#ifndef ALPHA_TLASER 646312Sgblack@eecs.umich.edu if (addr & PAddrUncachedBit43) { 657720Sgblack@eecs.umich.edu addr &= PAddrUncachedMask; 666312Sgblack@eecs.umich.edu addr |= PAddrUncachedBit40; 677186Sgblack@eecs.umich.edu } 687720Sgblack@eecs.umich.edu#endif 697186Sgblack@eecs.umich.edu return addr | AlphaISA::K0SegBase; 707186Sgblack@eecs.umich.edu} 716312Sgblack@eecs.umich.edu 727093Sgblack@eecs.umich.eduinline int DTB_ASN_ASN(uint64_t reg) { return reg >> 57 & AsnMask; } 736312Sgblack@eecs.umich.eduinline Addr DTB_PTE_PPN(uint64_t reg) 746312Sgblack@eecs.umich.edu{ return reg >> 32 & (ULL(1) << PAddrImplBits - AlphaISA::PageShift) - 1; } 757148Sgblack@eecs.umich.eduinline int DTB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; } 767148Sgblack@eecs.umich.eduinline int DTB_PTE_XWE(uint64_t reg) { return reg >> 12 & 0xf; } 777148Sgblack@eecs.umich.eduinline int DTB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; } 787148Sgblack@eecs.umich.eduinline int DTB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; } 797184Sgblack@eecs.umich.eduinline int DTB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; } 807184Sgblack@eecs.umich.eduinline int DTB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; } 817289Sgblack@eecs.umich.edu 827289Sgblack@eecs.umich.eduinline int ITB_ASN_ASN(uint64_t reg) { return reg >> 4 & AsnMask; } 837289Sgblack@eecs.umich.eduinline Addr ITB_PTE_PPN(uint64_t reg) 847289Sgblack@eecs.umich.edu{ return reg >> 32 & (ULL(1) << PAddrImplBits - AlphaISA::PageShift) - 1; } 857184Sgblack@eecs.umich.eduinline int ITB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; } 867184Sgblack@eecs.umich.eduinline bool ITB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; } 877184Sgblack@eecs.umich.eduinline bool ITB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; } 887184Sgblack@eecs.umich.eduinline int ITB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; } 897184Sgblack@eecs.umich.eduinline bool ITB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; } 907184Sgblack@eecs.umich.edu 9110037SARM gem5 Developersinline uint64_t MCSR_SP(uint64_t reg) { return reg >> 1 & 0x3; } 9210037SARM gem5 Developers 9310037SARM gem5 Developersinline bool ICSR_SDE(uint64_t reg) { return reg >> 30 & 0x1; } 9410037SARM gem5 Developersinline int ICSR_SPE(uint64_t reg) { return reg >> 28 & 0x3; } 9510037SARM gem5 Developersinline bool ICSR_FPE(uint64_t reg) { return reg >> 26 & 0x1; } 9610037SARM gem5 Developers 9710037SARM gem5 Developersinline uint64_t ALT_MODE_AM(uint64_t reg) { return reg >> 3 & 0x3; } 9810037SARM gem5 Developersinline uint64_t DTB_CM_CM(uint64_t reg) { return reg >> 3 & 0x3; } 9910037SARM gem5 Developersinline uint64_t ICM_CM(uint64_t reg) { return reg >> 3 & 0x3; } 10010037SARM gem5 Developers 10110037SARM gem5 Developersconst uint64_t MM_STAT_BAD_VA_MASK = ULL(0x0020); 10210037SARM gem5 Developersconst uint64_t MM_STAT_DTB_MISS_MASK = ULL(0x0010); 10310037SARM gem5 Developersconst uint64_t MM_STAT_FONW_MASK = ULL(0x0008); 10410037SARM gem5 Developersconst uint64_t MM_STAT_FONR_MASK = ULL(0x0004); 10510037SARM gem5 Developersconst uint64_t MM_STAT_ACV_MASK = ULL(0x0002); 10610037SARM gem5 Developersconst uint64_t MM_STAT_WR_MASK = ULL(0x0001); 10710037SARM gem5 Developersinline int Opcode(AlphaISA::MachInst inst) { return inst >> 26 & 0x3f; } 10810037SARM gem5 Developersinline int Ra(AlphaISA::MachInst inst) { return inst >> 21 & 0x1f; } 10910037SARM gem5 Developers 11012499Sgiacomo.travaglini@arm.comconst Addr PalBase = 0x4000; 11110037SARM gem5 Developersconst Addr PalMax = 0x10000; 11210037SARM gem5 Developers 11310037SARM gem5 Developers/* namespace EV5 */ } 11412499Sgiacomo.travaglini@arm.com 11510037SARM gem5 Developers#endif // __ARCH_ALPHA_EV5_HH__ 1167797Sgblack@eecs.umich.edu