ev5.hh revision 5566
11689SN/A/* 22326SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 291689SN/A * Nathan Binkert 301689SN/A * Ali Saidi 311060SN/A */ 321060SN/A 331689SN/A#ifndef __ARCH_ALPHA_EV5_HH__ 341060SN/A#define __ARCH_ALPHA_EV5_HH__ 351060SN/A 361060SN/A#include "config/alpha_tlaser.hh" 371060SN/A#include "arch/alpha/isa_traits.hh" 382292SN/A 391717SN/Anamespace AlphaISA { 401060SN/A 411681SN/A#if ALPHA_TLASER 422292SN/Aconst uint64_t AsnMask = ULL(0x7f); 432873Sktlim@umich.edu#else 441060SN/Aconst uint64_t AsnMask = ULL(0xff); 451061SN/A#endif 462292SN/A 472292SN/Aconst int VAddrImplBits = 43; 482292SN/Aconst Addr VAddrImplMask = (ULL(1) << VAddrImplBits) - 1; 492292SN/Aconst Addr VAddrUnImplMask = ~VAddrImplMask; 502820Sktlim@umich.eduinline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; } 512292SN/Ainline Addr VAddrVPN(Addr a) { return a >> AlphaISA::PageShift; } 522820Sktlim@umich.eduinline Addr VAddrOffset(Addr a) { return a & AlphaISA::PageOffset; } 532820Sktlim@umich.eduinline Addr VAddrSpaceEV5(Addr a) { return a >> 41 & 0x3; } 542307SN/Ainline Addr VAddrSpaceEV6(Addr a) { return a >> 41 & 0x7f; } 552307SN/A 561060SN/A#if ALPHA_TLASER 572292SN/Ainline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFF00000); } 582292SN/Aconst int PAddrImplBits = 40; 592292SN/A#else 601060SN/Ainline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFFF00000); } 611060SN/Aconst int PAddrImplBits = 44; // for Tsunami 621060SN/A#endif 631060SN/Aconst Addr PAddrImplMask = (ULL(1) << PAddrImplBits) - 1; 641060SN/Aconst Addr PAddrUncachedBit39 = ULL(0x8000000000); 651060SN/Aconst Addr PAddrUncachedBit40 = ULL(0x10000000000); 661681SN/Aconst Addr PAddrUncachedBit43 = ULL(0x80000000000); 672292SN/Aconst Addr PAddrUncachedMask = ULL(0x807ffffffff); // Clear PA<42:35> 681681SN/Ainline Addr Phys2K0Seg(Addr addr) 692292SN/A{ 702292SN/A#if !ALPHA_TLASER 712292SN/A if (addr & PAddrUncachedBit43) { 722292SN/A addr &= PAddrUncachedMask; 732292SN/A addr |= PAddrUncachedBit40; 742935Sksewell@umich.edu } 752292SN/A#endif 762292SN/A return addr | AlphaISA::K0SegBase; 772820Sktlim@umich.edu} 782820Sktlim@umich.edu 792292SN/Ainline int DTB_ASN_ASN(uint64_t reg) { return reg >> 57 & AsnMask; } 802292SN/Ainline Addr DTB_PTE_PPN(uint64_t reg) 812820Sktlim@umich.edu{ return reg >> 32 & (ULL(1) << PAddrImplBits - AlphaISA::PageShift) - 1; } 822820Sktlim@umich.eduinline int DTB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; } 832292SN/Ainline int DTB_PTE_XWE(uint64_t reg) { return reg >> 12 & 0xf; } 842292SN/Ainline int DTB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; } 852292SN/Ainline int DTB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; } 862292SN/Ainline int DTB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; } 872292SN/Ainline int DTB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; } 882292SN/A 892292SN/Ainline int ITB_ASN_ASN(uint64_t reg) { return reg >> 4 & AsnMask; } 902292SN/Ainline Addr ITB_PTE_PPN(uint64_t reg) 911060SN/A{ return reg >> 32 & (ULL(1) << PAddrImplBits - AlphaISA::PageShift) - 1; } 921060SN/Ainline int ITB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; } 931681SN/Ainline bool ITB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; } 941062SN/Ainline bool ITB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; } 952292SN/Ainline int ITB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; } 961062SN/Ainline bool ITB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; } 972301SN/A 982301SN/Ainline uint64_t MCSR_SP(uint64_t reg) { return reg >> 1 & 0x3; } 991062SN/A 1002727Sktlim@umich.eduinline bool ICSR_SDE(uint64_t reg) { return reg >> 30 & 0x1; } 1011062SN/Ainline int ICSR_SPE(uint64_t reg) { return reg >> 28 & 0x3; } 1021062SN/Ainline bool ICSR_FPE(uint64_t reg) { return reg >> 26 & 0x1; } 1031062SN/A 1041062SN/Ainline uint64_t ALT_MODE_AM(uint64_t reg) { return reg >> 3 & 0x3; } 1051062SN/Ainline uint64_t DTB_CM_CM(uint64_t reg) { return reg >> 3 & 0x3; } 1061062SN/Ainline uint64_t ICM_CM(uint64_t reg) { return reg >> 3 & 0x3; } 1071062SN/A 1081062SN/Aconst uint64_t MM_STAT_BAD_VA_MASK = ULL(0x0020); 1091062SN/Aconst uint64_t MM_STAT_DTB_MISS_MASK = ULL(0x0010); 1101062SN/Aconst uint64_t MM_STAT_FONW_MASK = ULL(0x0008); 1111062SN/Aconst uint64_t MM_STAT_FONR_MASK = ULL(0x0004); 1121062SN/Aconst uint64_t MM_STAT_ACV_MASK = ULL(0x0002); 1131062SN/Aconst uint64_t MM_STAT_WR_MASK = ULL(0x0001); 1141062SN/Ainline int Opcode(AlphaISA::MachInst inst) { return inst >> 26 & 0x3f; } 1151062SN/Ainline int Ra(AlphaISA::MachInst inst) { return inst >> 21 & 0x1f; } 1161062SN/A 1171062SN/Aconst Addr PalBase = 0x4000; 1181062SN/Aconst Addr PalMax = 0x10000; 1191062SN/A 1201062SN/A} // namespace AlphaISA 1211062SN/A 1221062SN/A#endif // __ARCH_ALPHA_EV5_HH__ 1231062SN/A