ev5.hh revision 2665
12124SN/A/* 22124SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 35268Sksewell@umich.edu * All rights reserved. 45268Sksewell@umich.edu * 55268Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 65268Sksewell@umich.edu * modification, are permitted provided that the following conditions are 75268Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 85268Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 95268Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 105268Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 115268Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 125268Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 135268Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 145268Sksewell@umich.edu * this software without specific prior written permission. 155268Sksewell@umich.edu * 165268Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175268Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185268Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195268Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205268Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215268Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225268Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235268Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245268Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255268Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265268Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275268Sksewell@umich.edu * 285268Sksewell@umich.edu * Authors: Steve Reinhardt 295268Sksewell@umich.edu * Nathan Binkert 305268Sksewell@umich.edu * Ali Saidi 312022SN/A */ 322649Ssaidi@eecs.umich.edu 332649Ssaidi@eecs.umich.edu#ifndef __ARCH_ALPHA_EV5_HH__ 342706Sksewell@umich.edu#define __ARCH_ALPHA_EV5_HH__ 352649Ssaidi@eecs.umich.edu 362649Ssaidi@eecs.umich.edu#include "config/alpha_tlaser.hh" 372022SN/A#include "arch/alpha/isa_traits.hh" 382124SN/A 392124SN/Anamespace EV5 { 402124SN/A 412124SN/A//It seems like a safe assumption EV5 only applies to alpha 422124SN/Ausing namespace AlphaISA; 432124SN/A 442124SN/A#if ALPHA_TLASER 452124SN/Aconst uint64_t AsnMask = ULL(0x7f); 465736Snate@binkert.org#else 472124SN/Aconst uint64_t AsnMask = ULL(0xff); 482124SN/A#endif 492124SN/A 502124SN/Aconst int VAddrImplBits = 43; 512239SN/Aconst Addr VAddrImplMask = (ULL(1) << VAddrImplBits) - 1; 522124SN/Aconst Addr VAddrUnImplMask = ~VAddrImplMask; 532124SN/Ainline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; } 542124SN/Ainline Addr VAddrVPN(Addr a) { return a >> AlphaISA::PageShift; } 552124SN/Ainline Addr VAddrOffset(Addr a) { return a & AlphaISA::PageOffset; } 562124SN/Ainline Addr VAddrSpaceEV5(Addr a) { return a >> 41 & 0x3; } 572124SN/Ainline Addr VAddrSpaceEV6(Addr a) { return a >> 41 & 0x7f; } 582124SN/A 592124SN/A#if ALPHA_TLASER 605736Snate@binkert.orginline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFF00000); } 612742Sksewell@umich.educonst int PAddrImplBits = 40; 622022SN/A#else 632124SN/Ainline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFFF00000); } 642022SN/Aconst int PAddrImplBits = 44; // for Tsunami 652124SN/A#endif 662124SN/Aconst Addr PAddrImplMask = (ULL(1) << PAddrImplBits) - 1; 672022SN/Aconst Addr PAddrUncachedBit39 = ULL(0x8000000000); 682124SN/Aconst Addr PAddrUncachedBit40 = ULL(0x10000000000); 692124SN/Aconst Addr PAddrUncachedBit43 = ULL(0x80000000000); 702124SN/Aconst Addr PAddrUncachedMask = ULL(0x807ffffffff); // Clear PA<42:35> 712124SN/Ainline Addr Phys2K0Seg(Addr addr) 724661Sksewell@umich.edu{ 735736Snate@binkert.org#if !ALPHA_TLASER 742124SN/A if (addr & PAddrUncachedBit43) { 752124SN/A addr &= PAddrUncachedMask; 762742Sksewell@umich.edu addr |= PAddrUncachedBit40; 772742Sksewell@umich.edu } 782742Sksewell@umich.edu#endif 792742Sksewell@umich.edu return addr | AlphaISA::K0SegBase; 802742Sksewell@umich.edu} 812742Sksewell@umich.edu 822742Sksewell@umich.eduinline int DTB_ASN_ASN(uint64_t reg) { return reg >> 57 & AsnMask; } 832742Sksewell@umich.eduinline Addr DTB_PTE_PPN(uint64_t reg) 842742Sksewell@umich.edu{ return reg >> 32 & (ULL(1) << PAddrImplBits - AlphaISA::PageShift) - 1; } 852742Sksewell@umich.eduinline int DTB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; } 862742Sksewell@umich.eduinline int DTB_PTE_XWE(uint64_t reg) { return reg >> 12 & 0xf; } 872742Sksewell@umich.eduinline int DTB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; } 882742Sksewell@umich.eduinline int DTB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; } 892742Sksewell@umich.eduinline int DTB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; } 902742Sksewell@umich.eduinline int DTB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; } 912742Sksewell@umich.edu 922742Sksewell@umich.eduinline int ITB_ASN_ASN(uint64_t reg) { return reg >> 4 & AsnMask; } 932742Sksewell@umich.eduinline Addr ITB_PTE_PPN(uint64_t reg) 942022SN/A{ return reg >> 32 & (ULL(1) << PAddrImplBits - AlphaISA::PageShift) - 1; } 952022SN/Ainline int ITB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; } 962124SN/Ainline bool ITB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; } 972022SN/Ainline bool ITB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; } 982124SN/Ainline int ITB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; } 992124SN/Ainline bool ITB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; } 1002124SN/A 1012742Sksewell@umich.eduinline uint64_t MCSR_SP(uint64_t reg) { return reg >> 1 & 0x3; } 1022239SN/A 1032124SN/Ainline bool ICSR_SDE(uint64_t reg) { return reg >> 30 & 0x1; } 1042124SN/Ainline int ICSR_SPE(uint64_t reg) { return reg >> 28 & 0x3; } 1052742Sksewell@umich.eduinline bool ICSR_FPE(uint64_t reg) { return reg >> 26 & 0x1; } 1062742Sksewell@umich.edu 1072742Sksewell@umich.eduinline uint64_t ALT_MODE_AM(uint64_t reg) { return reg >> 3 & 0x3; } 1082742Sksewell@umich.eduinline uint64_t DTB_CM_CM(uint64_t reg) { return reg >> 3 & 0x3; } 1092742Sksewell@umich.eduinline uint64_t ICM_CM(uint64_t reg) { return reg >> 3 & 0x3; } 1102742Sksewell@umich.edu 1112742Sksewell@umich.educonst uint64_t MM_STAT_BAD_VA_MASK = ULL(0x0020); 1122742Sksewell@umich.educonst uint64_t MM_STAT_DTB_MISS_MASK = ULL(0x0010); 1134661Sksewell@umich.educonst uint64_t MM_STAT_FONW_MASK = ULL(0x0008); 1144661Sksewell@umich.educonst uint64_t MM_STAT_FONR_MASK = ULL(0x0004); 1154661Sksewell@umich.educonst uint64_t MM_STAT_ACV_MASK = ULL(0x0002); 1164661Sksewell@umich.educonst uint64_t MM_STAT_WR_MASK = ULL(0x0001); 1174661Sksewell@umich.eduinline int Opcode(AlphaISA::MachInst inst) { return inst >> 26 & 0x3f; } 1184661Sksewell@umich.eduinline int Ra(AlphaISA::MachInst inst) { return inst >> 21 & 0x1f; } 1194661Sksewell@umich.edu 1205222Sksewell@umich.educonst Addr PalBase = 0x4000; 1214661Sksewell@umich.educonst Addr PalMax = 0x10000; 1224661Sksewell@umich.edu 1235222Sksewell@umich.edu/* namespace EV5 */ } 1244661Sksewell@umich.edu 1254661Sksewell@umich.edu#endif // __ARCH_ALPHA_EV5_HH__ 1265222Sksewell@umich.edu