ev5.hh revision 2107
13646Srdreslin@umich.edu/* 23646Srdreslin@umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 33646Srdreslin@umich.edu * All rights reserved. 43646Srdreslin@umich.edu * 53646Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without 63646Srdreslin@umich.edu * modification, are permitted provided that the following conditions are 73646Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright 83646Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer; 93646Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright 103646Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the 113646Srdreslin@umich.edu * documentation and/or other materials provided with the distribution; 123646Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its 133646Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 143646Srdreslin@umich.edu * this software without specific prior written permission. 153646Srdreslin@umich.edu * 163646Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173646Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183646Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193646Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203646Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213646Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223646Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233646Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243646Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253646Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263646Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273646Srdreslin@umich.edu */ 283646Srdreslin@umich.edu 293646Srdreslin@umich.edu#ifndef __ARCH_ALPHA_EV5_HH__ 303646Srdreslin@umich.edu#define __ARCH_ALPHA_EV5_HH__ 313646Srdreslin@umich.edu 323646Srdreslin@umich.edu#include "config/alpha_tlaser.hh" 333646Srdreslin@umich.edu#include "arch/alpha/isa_traits.hh" 343646Srdreslin@umich.edu 353646Srdreslin@umich.edunamespace EV5 { 363646Srdreslin@umich.edu 373646Srdreslin@umich.edu//It seems like a safe assumption EV5 only applies to alpha 383646Srdreslin@umich.eduusing namespace AlphaISA; 393646Srdreslin@umich.edu 403646Srdreslin@umich.edu#if ALPHA_TLASER 413646Srdreslin@umich.educonst uint64_t AsnMask = ULL(0x7f); 423646Srdreslin@umich.edu#else 433646Srdreslin@umich.educonst uint64_t AsnMask = ULL(0xff); 443646Srdreslin@umich.edu#endif 453646Srdreslin@umich.edu 463646Srdreslin@umich.educonst int VAddrImplBits = 43; 473646Srdreslin@umich.educonst Addr VAddrImplMask = (ULL(1) << VAddrImplBits) - 1; 483646Srdreslin@umich.educonst Addr VAddrUnImplMask = ~VAddrImplMask; 493646Srdreslin@umich.eduinline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; } 503646Srdreslin@umich.eduinline Addr VAddrVPN(Addr a) { return a >> AlphaISA::PageShift; } 513646Srdreslin@umich.eduinline Addr VAddrOffset(Addr a) { return a & AlphaISA::PageOffset; } 523646Srdreslin@umich.eduinline Addr VAddrSpaceEV5(Addr a) { return a >> 41 & 0x3; } 533646Srdreslin@umich.eduinline Addr VAddrSpaceEV6(Addr a) { return a >> 41 & 0x7f; } 543646Srdreslin@umich.edu 553646Srdreslin@umich.edu#if ALPHA_TLASER 563646Srdreslin@umich.eduinline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFF00000); } 573646Srdreslin@umich.educonst int PAddrImplBits = 40; 583646Srdreslin@umich.edu#else 593646Srdreslin@umich.eduinline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFFF00000); } 603646Srdreslin@umich.educonst int PAddrImplBits = 44; // for Tsunami 613646Srdreslin@umich.edu#endif 623646Srdreslin@umich.educonst Addr PAddrImplMask = (ULL(1) << PAddrImplBits) - 1; 633646Srdreslin@umich.educonst Addr PAddrUncachedBit39 = ULL(0x8000000000); 643646Srdreslin@umich.educonst Addr PAddrUncachedBit40 = ULL(0x10000000000); 653646Srdreslin@umich.educonst Addr PAddrUncachedBit43 = ULL(0x80000000000); 663646Srdreslin@umich.educonst Addr PAddrUncachedMask = ULL(0x807ffffffff); // Clear PA<42:35> 673646Srdreslin@umich.eduinline Addr Phys2K0Seg(Addr addr) 683646Srdreslin@umich.edu{ 693646Srdreslin@umich.edu#if !ALPHA_TLASER 703646Srdreslin@umich.edu if (addr & PAddrUncachedBit43) { 713646Srdreslin@umich.edu addr &= PAddrUncachedMask; 723646Srdreslin@umich.edu addr |= PAddrUncachedBit40; 733646Srdreslin@umich.edu } 743646Srdreslin@umich.edu#endif 753646Srdreslin@umich.edu return addr | AlphaISA::K0SegBase; 763646Srdreslin@umich.edu} 773646Srdreslin@umich.edu 783646Srdreslin@umich.eduinline int DTB_ASN_ASN(uint64_t reg) { return reg >> 57 & AsnMask; } 793646Srdreslin@umich.eduinline Addr DTB_PTE_PPN(uint64_t reg) 803646Srdreslin@umich.edu{ return reg >> 32 & (ULL(1) << PAddrImplBits - AlphaISA::PageShift) - 1; } 813646Srdreslin@umich.eduinline int DTB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; } 823646Srdreslin@umich.eduinline int DTB_PTE_XWE(uint64_t reg) { return reg >> 12 & 0xf; } 833646Srdreslin@umich.eduinline int DTB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; } 843646Srdreslin@umich.eduinline int DTB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; } 853646Srdreslin@umich.eduinline int DTB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; } 863646Srdreslin@umich.eduinline int DTB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; } 873646Srdreslin@umich.edu 883646Srdreslin@umich.eduinline int ITB_ASN_ASN(uint64_t reg) { return reg >> 4 & AsnMask; } 893646Srdreslin@umich.eduinline Addr ITB_PTE_PPN(uint64_t reg) 903646Srdreslin@umich.edu{ return reg >> 32 & (ULL(1) << PAddrImplBits - AlphaISA::PageShift) - 1; } 913646Srdreslin@umich.eduinline int ITB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; } 923646Srdreslin@umich.eduinline bool ITB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; } 933646Srdreslin@umich.eduinline bool ITB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; } 943646Srdreslin@umich.eduinline int ITB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; } 953646Srdreslin@umich.eduinline bool ITB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; } 963646Srdreslin@umich.edu 973646Srdreslin@umich.eduinline uint64_t MCSR_SP(uint64_t reg) { return reg >> 1 & 0x3; } 983646Srdreslin@umich.edu 993646Srdreslin@umich.eduinline bool ICSR_SDE(uint64_t reg) { return reg >> 30 & 0x1; } 1003646Srdreslin@umich.eduinline int ICSR_SPE(uint64_t reg) { return reg >> 28 & 0x3; } 1013646Srdreslin@umich.eduinline bool ICSR_FPE(uint64_t reg) { return reg >> 26 & 0x1; } 1023646Srdreslin@umich.edu 1033646Srdreslin@umich.eduinline uint64_t ALT_MODE_AM(uint64_t reg) { return reg >> 3 & 0x3; } 1043646Srdreslin@umich.eduinline uint64_t DTB_CM_CM(uint64_t reg) { return reg >> 3 & 0x3; } 1053646Srdreslin@umich.eduinline uint64_t ICM_CM(uint64_t reg) { return reg >> 3 & 0x3; } 1063646Srdreslin@umich.edu 1073646Srdreslin@umich.educonst uint64_t MM_STAT_BAD_VA_MASK = ULL(0x0020); 1083646Srdreslin@umich.educonst uint64_t MM_STAT_DTB_MISS_MASK = ULL(0x0010); 1093646Srdreslin@umich.educonst uint64_t MM_STAT_FONW_MASK = ULL(0x0008); 1103646Srdreslin@umich.educonst uint64_t MM_STAT_FONR_MASK = ULL(0x0004); 1113646Srdreslin@umich.educonst uint64_t MM_STAT_ACV_MASK = ULL(0x0002); 1123646Srdreslin@umich.educonst uint64_t MM_STAT_WR_MASK = ULL(0x0001); 1133646Srdreslin@umich.eduinline int Opcode(AlphaISA::MachInst inst) { return inst >> 26 & 0x3f; } 1143646Srdreslin@umich.eduinline int Ra(AlphaISA::MachInst inst) { return inst >> 21 & 0x1f; } 1153646Srdreslin@umich.edu 1163646Srdreslin@umich.educonst Addr PalBase = 0x4000; 1173646Srdreslin@umich.educonst Addr PalMax = 0x10000; 1183646Srdreslin@umich.edu 1193646Srdreslin@umich.edu/* namespace EV5 */ } 1203646Srdreslin@umich.edu 1213646Srdreslin@umich.edu#endif // __ARCH_ALPHA_EV5_HH__ 1223646Srdreslin@umich.edu