ev5.hh revision 1762
12330SN/A/* 22330SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32330SN/A * All rights reserved. 42330SN/A * 52330SN/A * Redistribution and use in source and binary forms, with or without 62330SN/A * modification, are permitted provided that the following conditions are 72330SN/A * met: redistributions of source code must retain the above copyright 82330SN/A * notice, this list of conditions and the following disclaimer; 92330SN/A * redistributions in binary form must reproduce the above copyright 102330SN/A * notice, this list of conditions and the following disclaimer in the 112330SN/A * documentation and/or other materials provided with the distribution; 122330SN/A * neither the name of the copyright holders nor the names of its 132330SN/A * contributors may be used to endorse or promote products derived from 142330SN/A * this software without specific prior written permission. 152330SN/A * 162330SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172330SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182330SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192330SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202330SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212330SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222330SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232330SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242330SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252330SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262330SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272689Sktlim@umich.edu */ 282689Sktlim@umich.edu 292330SN/A#ifndef __ARCH_ALPHA_EV5_HH__ 302292SN/A#define __ARCH_ALPHA_EV5_HH__ 312292SN/A 322292SN/Anamespace EV5 { 332292SN/A 342980Sgblack@eecs.umich.edu#ifdef ALPHA_TLASER 352362SN/Aconst uint64_t AsnMask = ULL(0x7f); 362680Sktlim@umich.edu#else 372292SN/Aconst uint64_t AsnMask = ULL(0xff); 382678Sktlim@umich.edu#endif 392683Sktlim@umich.edu 402678Sktlim@umich.educonst int VAddrImplBits = 43; 412683Sktlim@umich.educonst Addr VAddrImplMask = (ULL(1) << VAddrImplBits) - 1; 422678Sktlim@umich.educonst Addr VAddrUnImplMask = ~VAddrImplMask; 432678Sktlim@umich.eduinline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; } 442292SN/Ainline Addr VAddrVPN(Addr a) { return a >> AlphaISA::PageShift; } 452292SN/Ainline Addr VAddrOffset(Addr a) { return a & AlphaISA::PageOffset; } 462292SN/Ainline Addr VAddrSpaceEV5(Addr a) { return a >> 41 & 0x3; } 472292SN/Ainline Addr VAddrSpaceEV6(Addr a) { return a >> 41 & 0x7f; } 482330SN/A 492330SN/A#ifdef ALPHA_TLASER 502330SN/Ainline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFF00000); } 512292SN/Aconst int PAddrImplBits = 40; 522292SN/A#else 532862Sktlim@umich.eduinline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFFF00000); } 542862Sktlim@umich.educonst int PAddrImplBits = 44; // for Tsunami 552330SN/A#endif 562330SN/Aconst Addr PAddrImplMask = (ULL(1) << PAddrImplBits) - 1; 572330SN/Aconst Addr PAddrUncachedBit39 = ULL(0x8000000000); 582330SN/Aconst Addr PAddrUncachedBit40 = ULL(0x10000000000); 592330SN/Aconst Addr PAddrUncachedBit43 = ULL(0x80000000000); 602330SN/Aconst Addr PAddrUncachedMask = ULL(0x807ffffffff); // Clear PA<42:35> 612292SN/A 622683Sktlim@umich.eduinline int DTB_ASN_ASN(uint64_t reg) { return reg >> 57 & AsnMask; } 632683Sktlim@umich.eduinline Addr DTB_PTE_PPN(uint64_t reg) 642292SN/A{ return reg >> 32 & (ULL(1) << PAddrImplBits - AlphaISA::PageShift) - 1; } 652683Sktlim@umich.eduinline int DTB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; } 662292SN/Ainline int DTB_PTE_XWE(uint64_t reg) { return reg >> 12 & 0xf; } 672791Sktlim@umich.eduinline int DTB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; } 682791Sktlim@umich.eduinline int DTB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; } 692292SN/Ainline int DTB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; } 702683Sktlim@umich.eduinline int DTB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; } 712862Sktlim@umich.edu 722862Sktlim@umich.eduinline int ITB_ASN_ASN(uint64_t reg) { return reg >> 4 & AsnMask; } 732862Sktlim@umich.eduinline Addr ITB_PTE_PPN(uint64_t reg) 742862Sktlim@umich.edu{ return reg >> 32 & (ULL(1) << PAddrImplBits - AlphaISA::PageShift) - 1; } 752683Sktlim@umich.eduinline int ITB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; } 762683Sktlim@umich.eduinline bool ITB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; } 772683Sktlim@umich.eduinline bool ITB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; } 782683Sktlim@umich.eduinline int ITB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; } 792683Sktlim@umich.eduinline bool ITB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; } 802683Sktlim@umich.edu 812683Sktlim@umich.eduinline uint64_t MCSR_SP(uint64_t reg) { return reg >> 1 & 0x3; } 822683Sktlim@umich.edu 832683Sktlim@umich.eduinline bool ICSR_SDE(uint64_t reg) { return reg >> 30 & 0x1; } 842683Sktlim@umich.eduinline int ICSR_SPE(uint64_t reg) { return reg >> 28 & 0x3; } 852683Sktlim@umich.eduinline bool ICSR_FPE(uint64_t reg) { return reg >> 26 & 0x1; } 862683Sktlim@umich.edu 872683Sktlim@umich.eduinline uint64_t ALT_MODE_AM(uint64_t reg) { return reg >> 3 & 0x3; } 882683Sktlim@umich.eduinline uint64_t DTB_CM_CM(uint64_t reg) { return reg >> 3 & 0x3; } 892683Sktlim@umich.eduinline uint64_t ICM_CM(uint64_t reg) { return reg >> 3 & 0x3; } 902683Sktlim@umich.edu 912683Sktlim@umich.educonst uint64_t MM_STAT_BAD_VA_MASK = ULL(0x0020); 922683Sktlim@umich.educonst uint64_t MM_STAT_DTB_MISS_MASK = ULL(0x0010); 932683Sktlim@umich.educonst uint64_t MM_STAT_FONW_MASK = ULL(0x0008); 942683Sktlim@umich.educonst uint64_t MM_STAT_FONR_MASK = ULL(0x0004); 952683Sktlim@umich.educonst uint64_t MM_STAT_ACV_MASK = ULL(0x0002); 962683Sktlim@umich.educonst uint64_t MM_STAT_WR_MASK = ULL(0x0001); 972683Sktlim@umich.eduinline int Opcode(AlphaISA::MachInst inst) { return inst >> 26 & 0x3f; } 982690Sktlim@umich.eduinline int Ra(AlphaISA::MachInst inst) { return inst >> 21 & 0x1f; } 992690Sktlim@umich.edu 1002683Sktlim@umich.educonst Addr PalBase = 0x4000; 1012683Sktlim@umich.educonst Addr PalMax = 0x10000; 1022690Sktlim@umich.edu 1032690Sktlim@umich.edu/* namespace EV5 */ } 1042683Sktlim@umich.edu 1052683Sktlim@umich.edu#endif // __ARCH_ALPHA_EV5_HH__ 1062683Sktlim@umich.edu