ev5.hh revision 1758
18706Sandreas.hansson@arm.com/* 28706Sandreas.hansson@arm.com * Copyright (c) 2002-2004 The Regents of The University of Michigan 38706Sandreas.hansson@arm.com * All rights reserved. 48706Sandreas.hansson@arm.com * 58706Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 68706Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 78706Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 88706Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 98706Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 108706Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 118706Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 128706Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its 136892SBrad.Beckmann@amd.com * contributors may be used to endorse or promote products derived from 146892SBrad.Beckmann@amd.com * this software without specific prior written permission. 156892SBrad.Beckmann@amd.com * 166892SBrad.Beckmann@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176892SBrad.Beckmann@amd.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186892SBrad.Beckmann@amd.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196892SBrad.Beckmann@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206892SBrad.Beckmann@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216892SBrad.Beckmann@amd.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226892SBrad.Beckmann@amd.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236892SBrad.Beckmann@amd.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246892SBrad.Beckmann@amd.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256892SBrad.Beckmann@amd.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266892SBrad.Beckmann@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276892SBrad.Beckmann@amd.com */ 286892SBrad.Beckmann@amd.com 296892SBrad.Beckmann@amd.com#ifndef __ARCH_ALPHA_EV5_HH__ 306892SBrad.Beckmann@amd.com#define __ARCH_ALPHA_EV5_HH__ 316892SBrad.Beckmann@amd.com 326892SBrad.Beckmann@amd.comnamespace EV5 { 336892SBrad.Beckmann@amd.com 346892SBrad.Beckmann@amd.com#ifdef ALPHA_TLASER 356892SBrad.Beckmann@amd.comconst uint64_t AsnMask = ULL(0x7f); 366892SBrad.Beckmann@amd.com#else 376892SBrad.Beckmann@amd.comconst uint64_t AsnMask = ULL(0xff); 386892SBrad.Beckmann@amd.com#endif 396892SBrad.Beckmann@amd.com 406892SBrad.Beckmann@amd.comconst int VAddrImplBits = 43; 416892SBrad.Beckmann@amd.comconst Addr VAddrImplMask = (ULL(1) << VAddrImplBits) - 1; 427563SBrad.Beckmann@amd.comconst Addr VAddrUnImplMask = ~VAddrImplMask; 436892SBrad.Beckmann@amd.cominline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; } 446892SBrad.Beckmann@amd.cominline Addr VAddrVPN(Addr a) { return a >> AlphaISA::PageShift; } 456892SBrad.Beckmann@amd.cominline Addr VAddrOffset(Addr a) { return a & AlphaISA::PageOffset; } 466892SBrad.Beckmann@amd.cominline Addr VAddrSpaceEV5(Addr a) { return a >> 41 & 0x3; } 477538SBrad.Beckmann@amd.cominline Addr VAddrSpaceEV6(Addr a) { return a >> 41 & 0x7f; } 488939SBrad.Beckmann@amd.com 498939SBrad.Beckmann@amd.com#ifdef ALPHA_TLASER 508939SBrad.Beckmann@amd.cominline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFF00000); } 517538SBrad.Beckmann@amd.comconst int PAddrImplBits = 40; 527538SBrad.Beckmann@amd.com#else 537538SBrad.Beckmann@amd.cominline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFFF00000); } 547538SBrad.Beckmann@amd.comconst int PAddrImplBits = 44; // for Tsunami 557538SBrad.Beckmann@amd.com#endif 567661Snate@binkert.orgconst Addr PAddrImplMask = (ULL(1) << PAddrImplBits) - 1; 577538SBrad.Beckmann@amd.comconst Addr PAddrUncachedBit39 = ULL(0x8000000000); 588612Stushar@csail.mit.educonst Addr PAddrUncachedBit40 = ULL(0x10000000000); 598612Stushar@csail.mit.educonst Addr PAddrUncachedBit43 = ULL(0x80000000000); 607538SBrad.Beckmann@amd.comconst Addr PAddrUncachedMask = ULL(0x807ffffffff); // Clear PA<42:35> 617538SBrad.Beckmann@amd.com 627917SBrad.Beckmann@amd.cominline int DTB_ASN_ASN(uint64_t reg) { return reg >> 57 & AsnMask; } 637563SBrad.Beckmann@amd.cominline Addr DTB_PTE_PPN(uint64_t reg) 647563SBrad.Beckmann@amd.com{ return reg >> 32 & (ULL(1) << PAddrImplBits - AlphaISA::PageShift) - 1; } 657538SBrad.Beckmann@amd.cominline int DTB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; } 667538SBrad.Beckmann@amd.cominline int DTB_PTE_XWE(uint64_t reg) { return reg >> 12 & 0xf; } 677538SBrad.Beckmann@amd.cominline int DTB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; } 687538SBrad.Beckmann@amd.cominline int DTB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; } 697538SBrad.Beckmann@amd.cominline int DTB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; } 707566SBrad.Beckmann@amd.cominline int DTB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; } 717566SBrad.Beckmann@amd.com 727809Snilay@cs.wisc.eduinline int ITB_ASN_ASN(uint64_t reg) { return reg >> 4 & AsnMask; } 737809Snilay@cs.wisc.eduinline Addr ITB_PTE_PPN(uint64_t reg) 747809Snilay@cs.wisc.edu{ return reg >> 32 & (ULL(1) << PAddrImplBits - AlphaISA::PageShift) - 1; } 757809Snilay@cs.wisc.eduinline int ITB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; } 768638Sglohinline bool ITB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; } 778638Sglohinline bool ITB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; } 787538SBrad.Beckmann@amd.cominline int ITB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; } 797538SBrad.Beckmann@amd.cominline bool ITB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; } 807538SBrad.Beckmann@amd.com 817538SBrad.Beckmann@amd.cominline uint64_t MCSR_SP(uint64_t reg) { return reg >> 1 & 0x3; } 829100SBrad.Beckmann@amd.com 839100SBrad.Beckmann@amd.cominline bool ICSR_SDE(uint64_t reg) { return reg >> 30 & 0x1; } 849100SBrad.Beckmann@amd.cominline int ICSR_SPE(uint64_t reg) { return reg >> 28 & 0x3; } 859100SBrad.Beckmann@amd.cominline bool ICSR_FPE(uint64_t reg) { return reg >> 26 & 0x1; } 869100SBrad.Beckmann@amd.com 879100SBrad.Beckmann@amd.cominline uint64_t ALT_MODE_AM(uint64_t reg) { return reg >> 3 & 0x3; } 889100SBrad.Beckmann@amd.cominline uint64_t DTB_CM_CM(uint64_t reg) { return reg >> 3 & 0x3; } 899100SBrad.Beckmann@amd.cominline uint64_t ICM_CM(uint64_t reg) { return reg >> 3 & 0x3; } 909100SBrad.Beckmann@amd.com 919100SBrad.Beckmann@amd.comconst uint64_t MM_STAT_BAD_VA_MASK = ULL(0x0020); 928929Snilay@cs.wisc.educonst uint64_t MM_STAT_DTB_MISS_MASK = ULL(0x0010); 936892SBrad.Beckmann@amd.comconst uint64_t MM_STAT_FONW_MASK = ULL(0x0008); 948638Sglohconst uint64_t MM_STAT_FONR_MASK = ULL(0x0004); 958690Snilay@cs.wisc.educonst uint64_t MM_STAT_ACV_MASK = ULL(0x0002); 968690Snilay@cs.wisc.educonst uint64_t MM_STAT_WR_MASK = ULL(0x0001); 978436SBrad.Beckmann@amd.cominline int Opcode(AlphaISA::MachInst inst) { return inst >> 26 & 0x3f; } 988436SBrad.Beckmann@amd.cominline int Ra(AlphaISA::MachInst inst) { return inst >> 21 & 0x1f; } 997032SBrad.Beckmann@amd.com 1007032SBrad.Beckmann@amd.comconst Addr PalBase = 0x4000; 1016923SBrad.Beckmann@amd.comconst Addr PalMax = 0x10000; 1029100SBrad.Beckmann@amd.com 1038929Snilay@cs.wisc.edu/* namespace EV5 */ } 1047557SBrad.Beckmann@amd.com 1056923SBrad.Beckmann@amd.com#endif // __ARCH_ALPHA_EV5_HH__ 1066923SBrad.Beckmann@amd.com