ev5.hh revision 1147
12SN/A/* $Id$ */ 21762SN/A 32SN/A#ifndef __ARCH_ALPHA_EV5_HH__ 42SN/A#define __ARCH_ALPHA_EV5_HH__ 52SN/A 62SN/Anamespace EV5 { 72SN/A 82SN/A#ifdef ALPHA_TLASER 92SN/Aconst uint64_t AsnMask = ULL(0x7f); 102SN/A#else 112SN/Aconst uint64_t AsnMask = ULL(0xff); 122SN/A#endif 132SN/A 142SN/Aconst int VAddrImplBits = 43; 152SN/Aconst Addr VAddrImplMask = (ULL(1) << VAddrImplBits) - 1; 162SN/Aconst Addr VAddrUnImplMask = ~VAddrImplMask; 172SN/Ainline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; } 182SN/Ainline Addr VAddrVPN(Addr a) { return a >> AlphaISA::PageShift; } 192SN/Ainline Addr VAddrOffset(Addr a) { return a & AlphaISA::PageOffset; } 202SN/Ainline Addr VAddrSpaceEV5(Addr a) { return a >> 41 & 0x3; } 212SN/Ainline Addr VAddrSpaceEV6(Addr a) { return a >> 41 & 0x7f; } 222SN/A 232SN/A#ifdef ALPHA_TLASER 242SN/Ainline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFF00000); } 252SN/Aconst int PAddrImplBits = 40; 262SN/A#else 272665SN/Ainline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFFF00000); } 282665SN/Aconst int PAddrImplBits = 44; // for Tsunami 292SN/A#endif 302SN/Aconst Addr PAddrImplMask = (ULL(1) << PAddrImplBits) - 1; 312SN/Aconst Addr PAddrUncachedBit39 = ULL(0x8000000000); 322SN/Aconst Addr PAddrUncachedBit40 = ULL(0x10000000000); 332SN/Aconst Addr PAddrUncachedBit43 = ULL(0x80000000000); 342SN/Aconst Addr PAddrUncachedMask = ULL(0x807ffffffff); // Clear PA<42:35> 352SN/A 3611263Sandreas.sandberg@arm.cominline int DTB_ASN_ASN(uint64_t reg) { return reg >> 57 & AsnMask; } 3711263Sandreas.sandberg@arm.cominline Addr DTB_PTE_PPN(uint64_t reg) 382SN/A{ return reg >> 32 & (ULL(1) << PAddrImplBits - AlphaISA::PageShift) - 1; } 392SN/Ainline int DTB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; } 402SN/Ainline int DTB_PTE_XWE(uint64_t reg) { return reg >> 12 & 0xf; } 4111263Sandreas.sandberg@arm.cominline int DTB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; } 4213770Sgabeblack@google.cominline int DTB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; } 432SN/Ainline int DTB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; } 442SN/Ainline int DTB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; } 452SN/A 462SN/Ainline int ITB_ASN_ASN(uint64_t reg) { return reg >> 4 & AsnMask; } 472SN/Ainline Addr ITB_PTE_PPN(uint64_t reg) 482SN/A{ return reg >> 32 & (ULL(1) << PAddrImplBits - AlphaISA::PageShift) - 1; } 4913770Sgabeblack@google.cominline int ITB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; } 502SN/Ainline bool ITB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; } 512SN/Ainline bool ITB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; } 524981SN/Ainline int ITB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; } 532SN/Ainline bool ITB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; } 542SN/A 552SN/Ainline uint64_t MCSR_SP(uint64_t reg) { return reg >> 1 & 0x3; } 5613770Sgabeblack@google.com 5713770Sgabeblack@google.cominline bool ICSR_SDE(uint64_t reg) { return reg >> 30 & 0x1; } 582SN/Ainline int ICSR_SPE(uint64_t reg) { return reg >> 28 & 0x3; } 592SN/Ainline bool ICSR_FPE(uint64_t reg) { return reg >> 26 & 0x1; } 604981SN/A 614981SN/Ainline uint64_t ALT_MODE_AM(uint64_t reg) { return reg >> 3 & 0x3; } 624981SN/Ainline uint64_t DTB_CM_CM(uint64_t reg) { return reg >> 3 & 0x3; } 632SN/Ainline uint64_t ICM_CM(uint64_t reg) { return reg >> 3 & 0x3; } 644981SN/A 651152SN/Aconst uint64_t MM_STAT_BAD_VA_MASK = ULL(0x0020); 662SN/Aconst uint64_t MM_STAT_DTB_MISS_MASK = ULL(0x0010); 672SN/Aconst uint64_t MM_STAT_FONW_MASK = ULL(0x0008); 681152SN/Aconst uint64_t MM_STAT_FONR_MASK = ULL(0x0004); 692566SN/Aconst uint64_t MM_STAT_ACV_MASK = ULL(0x0002); 701152SN/Aconst uint64_t MM_STAT_WR_MASK = ULL(0x0001); 712566SN/Ainline int Opcode(AlphaISA::MachInst inst) { return inst >> 26 & 0x3f; } 724419SN/Ainline int Ra(AlphaISA::MachInst inst) { return inst >> 21 & 0x1f; } 734419SN/A 744419SN/Aconst Addr PalBase = 0x4000; 752SN/Aconst Addr PalMax = 0x10000; 762SN/A 7711263Sandreas.sandberg@arm.com/* namespace EV5 */ } 78 79#endif // __ARCH_ALPHA_EV5_HH__ 80