test6_arm_4c.py revision 11314:4a5f52f2defa
1# Copyright (c)2015 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Redistribution and use in source and binary forms, with or without 14# modification, are permitted provided that the following conditions are 15# met: redistributions of source code must retain the above copyright 16# notice, this list of conditions and the following disclaimer; 17# redistributions in binary form must reproduce the above copyright 18# notice, this list of conditions and the following disclaimer in the 19# documentation and/or other materials provided with the distribution; 20# neither the name of the copyright holders nor the names of its 21# contributors may be used to endorse or promote products derived from 22# this software without specific prior written permission. 23# 24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# 36# Authors: Curtis Dunham 37 38import sst 39import sys 40import os 41 42lat="1 ns" 43buslat="2 ns" 44clockRate = "1GHz" 45 46 47def getenv(name): 48 res = "" 49 try: 50 res = os.environ[name] 51 except KeyError: 52 pass 53 return res 54 55baseCacheParams = ({ 56 "debug" :getenv("DEBUG"), 57 "debug_level" : 6, 58 "coherence_protocol" : "MSI", 59 "replacement_policy" : "LRU", 60 "cache_line_size" : 64, 61 "cache_frequency" : clockRate, 62 "statistics" : 1 63 }) 64 65l1CacheParams = ({ 66 "debug" : getenv("DEBUG"), 67 "debug_level" : 6, 68 "L1" : 1, 69 "cache_size" : "64 KB", 70 "associativity" : 4, 71 "access_latency_cycles" : 2, 72 "low_network_links" : 1 73 }) 74 75l2CacheParams = ({ 76 "debug" : getenv("DEBUG"), 77 "debug_level" : 6, 78 "L1" : 0, 79 "cache_size" : "256 KB", 80 "associativity" : 8, 81 "access_latency_cycles" : 8, 82 "high_network_links" : 1, 83 "mshr_num_entries" : 4096, 84 "low_network_links" : 1 85 }) 86 87 88GEM5 = sst.Component("system", "gem5.gem5") 89GEM5.addParams({ 90 "comp_debug" : getenv("GEM5_DEBUG"), 91 "gem5DebugFlags" : getenv("M5_DEBUG"), 92 "frequency" : clockRate, 93 "cmd" : "configs/example/fs.py --num-cpus 4 --disk-image=vexpress64-openembedded_minimal-armv8_20130623-376.img --root-device=/dev/sda2 --kernel=vmlinux.aarch64.20140821 --dtb-filename=vexpress.aarch64.20140821.dtb --mem-size=256MB --machine-type=VExpress_EMM64 --cpu-type=timing --external-memory-system=sst" 94 }) 95 96bus = sst.Component("membus", "memHierarchy.Bus") 97bus.addParams({ 98 "bus_frequency": "2GHz", 99 "debug" : getenv("DEBUG"), 100 "debug_level" : 8 101 }) 102 103def buildL1(name, m5, connector): 104 cache = sst.Component(name, "memHierarchy.Cache") 105 cache.addParams(baseCacheParams) 106 cache.addParams(l1CacheParams) 107 link = sst.Link("cpu_%s_link"%name) 108 link.connect((m5, connector, lat), (cache, "high_network_0", lat)) 109 return cache 110 111SysBusConn = buildL1("gem5SystemBus", GEM5, "system.external_memory.port") 112bus_port = 0 113link = sst.Link("sysbus_bus_link") 114link.connect((SysBusConn, "low_network_0", buslat), (bus, "high_network_%u" % bus_port, buslat)) 115 116bus_port = bus_port + 1 117ioCache = buildL1("ioCache", GEM5, "system.iocache.port") 118ioCache.addParams({ 119 "debug" : 0, 120 "debug_level" : 6, 121 "cache_size" : "16 KB", 122 "associativity" : 4 123 }) 124link = sst.Link("ioCache_bus_link") 125link.connect((ioCache, "low_network_0", buslat), (bus, "high_network_%u" % bus_port, buslat)) 126 127def buildCPU(m5, num): 128 l1iCache = buildL1("cpu%u.l1iCache" % num, m5, "system.cpu%u.icache.port" % num) 129 l1dCache = buildL1("cpu%u.l1dCache" % num, m5, "system.cpu%u.dcache.port" % num) 130 itlbCache = buildL1("cpu%u.itlbCache" % num, m5, "system.cpu%u.itb_walker_cache.port" % num) 131 dtlbCache = buildL1("cpu%u.dtlbCache" % num, m5, "system.cpu%u.dtb_walker_cache.port" % num) 132 l1dCache.addParams({ 133 "debug" : 0, 134 "debug_level" : 10, 135 "snoop_l1_invalidations" : 1 136 }) 137 138 global bus_port 139 link = sst.Link("cpu%u.l1iCache_bus_link" % num) ; bus_port = bus_port + 1 140 link.connect((l1iCache, "low_network_0", buslat), (bus, "high_network_%u" % bus_port, buslat)) 141 link = sst.Link("cpu%u.l1dCache_bus_link" % num) ; bus_port = bus_port + 1 142 link.connect((l1dCache, "low_network_0", buslat), (bus, "high_network_%u" % bus_port, buslat)) 143 link = sst.Link("cpu%u.itlbCache_bus_link" % num) ; bus_port = bus_port + 1 144 link.connect((itlbCache, "low_network_0", buslat), (bus, "high_network_%u" % bus_port, buslat)) 145 link = sst.Link("cpu%u.dtlbCache_bus_link" % num) ; bus_port = bus_port + 1 146 link.connect((dtlbCache, "low_network_0", buslat), (bus, "high_network_%u" % bus_port, buslat)) 147 148buildCPU(GEM5, 0) 149buildCPU(GEM5, 1) 150buildCPU(GEM5, 2) 151buildCPU(GEM5, 3) 152 153l2cache = sst.Component("l2cache", "memHierarchy.Cache") 154l2cache.addParams(baseCacheParams) 155l2cache.addParams(l2CacheParams) 156l2cache.addParams({ 157 "network_address" : "2", 158 "directory_at_next_level" : "1" 159}) 160 161link = sst.Link("l2cache_bus_link") 162link.connect((l2cache, "high_network_0", buslat), (bus, "low_network_0", buslat)) 163 164memory = sst.Component("memory", "memHierarchy.MemController") 165memory.addParams({ 166 "request_width" : 64, 167 "coherence_protocol" : "MSI", 168 "access_time" : "25 ns", 169 "backend.mem_size" : 256, 170 "clock" : "2GHz", 171 "debug" : getenv("DEBUG"), 172 "range_start" : 0, # 2 * (1024 ** 3), # it's behind a directory controller. 173 }) 174 175comp_chiprtr = sst.Component("chiprtr", "merlin.hr_router") 176comp_chiprtr.addParams({ 177 "xbar_bw" : "16GB/s", 178 "link_bw" : "16GB/s", 179 "input_buf_size" : "1KB", 180 "num_ports" : "3", 181 "flit_size" : "72B", 182 "output_buf_size" : "1KB", 183 "id" : "0", 184 "topology" : "merlin.singlerouter" 185}) 186comp_dirctrl = sst.Component("dirctrl", "memHierarchy.DirectoryController") 187comp_dirctrl.addParams({ 188 "coherence_protocol" : "MSI", 189 "network_address" : "1", 190 "entry_cache_size" : "16384", 191 "network_bw" : "1GB/s", 192 "addr_range_start" : 2 * (1024 ** 3), 193 "addr_range_end" : 2 * (1024 ** 3) + 256 * (1024 ** 2) 194}) 195 196sst.Link("link_cache_net_0").connect((l2cache, "directory", "10ns"), (comp_chiprtr, "port2", "2ns")) 197sst.Link("link_dir_net_0").connect((comp_chiprtr, "port1", "2ns"), (comp_dirctrl, "network", "2ns")) 198sst.Link("l2cache_io_link").connect((comp_chiprtr, "port0", "2ns"), (GEM5, "network", buslat)) 199sst.Link("link_dir_mem_link").connect((comp_dirctrl, "memory", "10ns"), (memory, "direct_link", "10ns")) 200