gem5.hh revision 10779 
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36// Copyright 2009-2014 Sandia Coporation.  Under the terms
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44
45#ifndef EXT_SST_GEM5_HH
46#define EXT_SST_GEM5_HH
47
48#include <string>
49#include <vector>
50
51#include <sst/core/serialization.h>
52#include <sst/core/component.h>
53#include <sst/core/output.h>
54
55#include <sim/simulate.hh>
56
57#include "ExtMaster.hh"
58#include "ExtSlave.hh"
59
60namespace SST {
61namespace gem5 {
62
63class gem5Component : public SST::Component,
64                      public ExternalSlave::Handler,
65                      public ExternalMaster::Handler {
66private:
67
68    Output dbg;
69    Output info;
70    uint64_t sim_cycles;
71    uint64_t clocks_processed;
72
73    std::vector<ExtMaster*> masters;
74    std::vector<ExtSlave*> slaves;
75
76    void splitCommandArgs(std::string &cmd, std::vector<char*> &args);
77    void initPython(int argc, char *argv[]);
78
79public:
80    gem5Component(ComponentId_t id, Params &params);
81    ~gem5Component();
82    virtual void init(unsigned);
83    virtual void setup();
84    virtual void finish();
85    bool clockTick(Cycle_t);
86
87    virtual ExternalMaster::Port *getExternalPort(
88        const std::string &name, ExternalMaster &owner,
89        const std::string &port_data);
90
91    virtual ExternalSlave::Port *getExternalPort(
92        const std::string &name, ExternalSlave &owner,
93        const std::string &port_data);
94};
95
96}
97}
98
99#endif
100