ExtSlave.hh revision 11617:a51ae096ca25
1// Copyright (c) 2015 ARM Limited 2// All rights reserved. 3// 4// The license below extends only to copyright in the software and shall 5// not be construed as granting a license to any other intellectual 6// property including but not limited to intellectual property relating 7// to a hardware implementation of the functionality of the software 8// licensed hereunder. You may use the software subject to the license 9// terms below provided that you ensure that this notice is replicated 10// unmodified and in its entirety in all distributions of the software, 11// modified or unmodified, in source code or in binary form. 12// 13// Redistribution and use in source and binary forms, with or without 14// modification, are permitted provided that the following conditions are 15// met: redistributions of source code must retain the above copyright 16// notice, this list of conditions and the following disclaimer; 17// redistributions in binary form must reproduce the above copyright 18// notice, this list of conditions and the following disclaimer in the 19// documentation and/or other materials provided with the distribution; 20// neither the name of the copyright holders nor the names of its 21// contributors may be used to endorse or promote products derived from 22// this software without specific prior written permission. 23// 24// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 36// Copyright 2009-2014 Sandia Coporation. Under the terms 37// of Contract DE-AC04-94AL85000 with Sandia Corporation, the U.S. 38// Government retains certain rights in this software. 39// 40// Copyright (c) 2009-2014, Sandia Corporation 41// All rights reserved. 42// 43// For license information, see the LICENSE file in the current directory. 44 45#ifndef EXT_SST_EXTSLAVE_HH 46#define EXT_SST_EXTSLAVE_HH 47 48#include <sst/core/component.h> 49#include <sst/core/output.h> 50#include <sst/core/interfaces/simpleMem.h> 51 52#include <sim/sim_object.hh> 53#include <mem/packet.hh> 54#include <mem/request.hh> 55#include <mem/external_slave.hh> 56 57namespace SST { 58class Link; 59class Event; 60class MemEvent; 61namespace gem5 { 62 63class gem5Component; 64 65class ExtSlave : public ExternalSlave::Port { 66 public: 67 const std::string name; 68 69 bool 70 recvTimingSnoopResp(PacketPtr packet) 71 { 72 fatal("recvTimingSnoopResp unimplemented"); 73 return false; 74 } 75 76 bool recvTimingReq(PacketPtr packet); 77 78 void recvFunctional(PacketPtr packet); 79 80 void recvRespRetry(); 81 82 Tick 83 recvAtomic(PacketPtr packet) 84 { 85 fatal("recvAtomic unimplemented"); 86 } 87 88 enum Phase { CONSTRUCTION, INIT, RUN }; 89 90 gem5Component *comp; 91 Output &out; 92 Phase simPhase; 93 94 std::list<MemEvent*>* initPackets; 95 Link* link; 96 std::list<PacketPtr> respQ; 97 bool blocked() { return !respQ.empty(); } 98 99 typedef std::map<Event::id_type, ::Packet*> PacketMap_t; 100 PacketMap_t PacketMap; // SST Event id -> gem5 Packet* 101 102public: 103 ExtSlave(gem5Component*, Output&, ExternalSlave&, std::string&); 104 void init(unsigned phase); 105 106 void 107 setup() 108 { 109 simPhase = RUN; 110 } 111 112 void handleEvent(Event*); 113}; 114 115} 116} 117 118#endif 119