1<?xml version="1.0" ?> 2<component id="root" name="root"> 3 <component id="system" name="system" type="System"> 4 <param name="core_tech_node" value="40"/> 5 <param name="target_core_clockrate" value="1400"/> 6 <param name="temperature" value="360"/> 7 <param name="interconnect_projection_type" value="0"/> 8 <param name="device_type" value="0"/> 9 <param name="machine_bits" value="64"/> 10 <param name="virtual_address_width" value="64"/> 11 <param name="physical_address_width" value="52"/> 12 <param name="virtual_memory_page_size" value="4096"/> 13 <param name="wire_is_mat_type" value="2"/> 14 <param name="wire_os_mat_type" value="2"/> 15 <param name="delay_wt" value="100"/> 16 <param name="area_wt" value="0"/> 17 <param name="dynamic_power_wt" value="100"/> 18 <param name="leakage_power_wt" value="0"/> 19 <param name="cycle_time_wt" value="0"/> 20 <param name="delay_dev" value="10000"/> 21 <param name="area_dev" value="10000"/> 22 <param name="dynamic_power_dev" value="10000"/> 23 <param name="leakage_power_dev" value="10000"/> 24 <param name="cycle_time_dev" value="10000"/> 25 <param name="ed" value="2"/> 26 <param name="burst_len" value="1"/> 27 <param name="int_prefetch_w" value="1"/> 28 <param name="page_sz_bits" value="0"/> 29 <param name="rpters_in_htree" value="1"/> 30 <param name="ver_htree_wires_over_array" value="0"/> 31 <param name="nuca" value="0"/> 32 <param name="nuca_bank_count" value="0"/> 33 <param name="force_cache_config" value="0"/> 34 <param name="wt" value="0"/> 35 <param name="force_wiretype" value="0"/> 36 <param name="print_detail" value="1"/> 37 <param name="add_ecc_b_" value="1"/> 38 <stat name="total_cycles" value="566948"/> 39 <component id="system.l1_cntrl0" name="l1_cntrl0" type="CacheController"> 40 <component id="system.l1_cntrl0.L1DcacheMemory" name="L1DcacheMemory" type="CacheUnit"> 41 <param name="level" value="1"/> 42 <param name="size" value="32768"/> 43 <param name="block_size" value="64"/> 44 <param name="assoc" value="2"/> 45 <param name="num_banks" value="1"/> 46 <param name="latency" value="2"/> 47 <param name="throughput" value="1"/> 48 <param name="miss_buffer_size" value="2"/> 49 <param name="fetch_buffer_size" value="2"/> 50 <param name="prefetch_buffer_size" value="2"/> 51 <param name="writeback_buffer_size" value="2"/> 52 <param name="clockrate" value="2000"/> 53 <param name="device_type" value="0"/> 54 <param name="tech_type" value="0"/> 55 <param name="Directory_type" value="2"/> 56 <param name="core_type" value="1"/> 57 <param name="wire_mat_type" value="2"/> 58 <param name="wire_type" value="0"/> 59 <param name="miss_buffer_assoc" value="0"/> 60 <param name="fetch_buffer_assoc" value="0"/> 61 <param name="prefetch_buffer_assoc" value="0"/> 62 <param name="writeback_buffer_assoc" value="0"/> 63 <param name="miss_buffer_banks" value="1"/> 64 <param name="fetch_buffer_banks" value="1"/> 65 <param name="prefetch_buffer_banks" value="1"/> 66 <param name="writeback_buffer_banks" value="1"/> 67 <param name="cache_access_mode" value="0"/> 68 <param name="miss_buff_access_mode" value="2"/> 69 <param name="fetch_buff_access_mode" value="2"/> 70 <param name="prefetch_buff_access_mode" value="2"/> 71 <param name="writeback_buff_access_mode"value="2"/> 72 <param name="cache_rw_ports" value="1"/> 73 <param name="cache_rd_ports" value="0"/> 74 <param name="cache_wr_ports" value="0"/> 75 <param name="cache_se_rd_ports" value="0"/> 76 <param name="cache_search_ports" value="0"/> 77 <param name="miss_buff_rw_ports" value="1"/> 78 <param name="miss_buff_rd_ports" value="0"/> 79 <param name="miss_buff_wr_ports" value="0"/> 80 <param name="miss_buff_se_rd_ports" value="0"/> 81 <param name="miss_buff_search_ports" value="1"/> 82 <param name="fetch_buff_rw_ports" value="1"/> 83 <param name="fetch_buff_rd_ports" value="0"/> 84 <param name="fetch_buff_wr_ports" value="0"/> 85 <param name="fetch_buff_se_rd_ports" value="0"/> 86 <param name="fetch_buff_search_ports" value="1"/> 87 <param name="pf_buff_rw_ports" value="1"/> 88 <param name="pf_buff_rd_ports" value="0"/> 89 <param name="pf_buff_wr_ports" value="0"/> 90 <param name="pf_buff_se_rd_ports" value="0"/> 91 <param name="pf_buff_search_ports" value="1"/> 92 <param name="wb_buff_rw_ports" value="1"/> 93 <param name="wb_buff_rd_ports" value="0"/> 94 <param name="wb_buff_wr_ports" value="0"/> 95 <param name="wb_buff_se_rd_ports" value="0"/> 96 <param name="wb_buff_search_ports" value="1"/> 97 <param name="pure_ram" value="0"/> 98 <stat name="num_data_array_reads" value="47291"/> 99 <stat name="num_data_array_writes" value="51619"/> 100 <stat name="num_tag_array_reads" value="91498"/> 101 <stat name="num_tag_array_writes" value="17078"/> 102 <stat name="read_misses" value="174"/> 103 <stat name="write_misses" value="12046"/> 104 <stat name="conflicts" value="12120"/> 105 <stat name="duty_cycle" value="1"/> 106 </component> 107 <component id="system.l1_cntrl0.L1IcacheMemory" name="L1IcacheMemory" type="CacheUnit"> 108 <param name="level" value="1"/> 109 <param name="size" value="32768"/> 110 <param name="block_size" value="64"/> 111 <param name="assoc" value="2"/> 112 <param name="num_banks" value="1"/> 113 <param name="latency" value="2"/> 114 <param name="throughput" value="1"/> 115 <param name="miss_buffer_size" value="2"/> 116 <param name="fetch_buffer_size" value="2"/> 117 <param name="prefetch_buffer_size" value="2"/> 118 <param name="writeback_buffer_size" value="2"/> 119 <param name="clockrate" value="2000"/> 120 <param name="device_type" value="0"/> 121 <param name="tech_type" value="0"/> 122 <param name="Directory_type" value="2"/> 123 <param name="core_type" value="1"/> 124 <param name="wire_mat_type" value="2"/> 125 <param name="wire_type" value="0"/> 126 <param name="miss_buffer_assoc" value="0"/> 127 <param name="fetch_buffer_assoc" value="0"/> 128 <param name="prefetch_buffer_assoc" value="0"/> 129 <param name="writeback_buffer_assoc" value="0"/> 130 <param name="miss_buffer_banks" value="1"/> 131 <param name="fetch_buffer_banks" value="1"/> 132 <param name="prefetch_buffer_banks" value="1"/> 133 <param name="writeback_buffer_banks" value="1"/> 134 <param name="cache_access_mode" value="0"/> 135 <param name="miss_buff_access_mode" value="2"/> 136 <param name="fetch_buff_access_mode" value="2"/> 137 <param name="prefetch_buff_access_mode" value="2"/> 138 <param name="writeback_buff_access_mode"value="2"/> 139 <param name="cache_rw_ports" value="1"/> 140 <param name="cache_rd_ports" value="0"/> 141 <param name="cache_wr_ports" value="0"/> 142 <param name="cache_se_rd_ports" value="0"/> 143 <param name="cache_search_ports" value="0"/> 144 <param name="miss_buff_rw_ports" value="1"/> 145 <param name="miss_buff_rd_ports" value="0"/> 146 <param name="miss_buff_wr_ports" value="0"/> 147 <param name="miss_buff_se_rd_ports" value="0"/> 148 <param name="miss_buff_search_ports" value="1"/> 149 <param name="fetch_buff_rw_ports" value="1"/> 150 <param name="fetch_buff_rd_ports" value="0"/> 151 <param name="fetch_buff_wr_ports" value="0"/> 152 <param name="fetch_buff_se_rd_ports" value="0"/> 153 <param name="fetch_buff_search_ports" value="1"/> 154 <param name="pf_buff_rw_ports" value="1"/> 155 <param name="pf_buff_rd_ports" value="0"/> 156 <param name="pf_buff_wr_ports" value="0"/> 157 <param name="pf_buff_se_rd_ports" value="0"/> 158 <param name="pf_buff_search_ports" value="1"/> 159 <param name="wb_buff_rw_ports" value="1"/> 160 <param name="wb_buff_rd_ports" value="0"/> 161 <param name="wb_buff_wr_ports" value="0"/> 162 <param name="wb_buff_se_rd_ports" value="0"/> 163 <param name="wb_buff_search_ports" value="1"/> 164 <param name="pure_ram" value="0"/> 165 <stat name="num_data_array_reads" value="253831"/> 166 <stat name="num_data_array_writes" value="3497"/> 167 <stat name="num_tag_array_reads" value="253291"/> 168 <stat name="num_tag_array_writes" value="10845"/> 169 <stat name="read_misses" value="100"/> 170 <stat name="conflicts" value="99"/> 171 <stat name="duty_cycle" value="1"/> 172 </component> 173 <component id="system.l1_cntrl0.L2cacheMemory" name="L2cacheMemory" type="CacheUnit"> 174 <param name="level" value="2"/> 175 <param name="size" value="2097152"/> 176 <param name="block_size" value="64"/> 177 <param name="assoc" value="16"/> 178 <param name="num_banks" value="1"/> 179 <param name="latency" value="10"/> 180 <param name="throughput" value="1"/> 181 <param name="miss_buffer_size" value="2"/> 182 <param name="fetch_buffer_size" value="2"/> 183 <param name="prefetch_buffer_size" value="2"/> 184 <param name="writeback_buffer_size" value="2"/> 185 <param name="clockrate" value="2000"/> 186 <param name="device_type" value="0"/> 187 <param name="tech_type" value="0"/> 188 <param name="Directory_type" value="2"/> 189 <param name="core_type" value="1"/> 190 <param name="wire_mat_type" value="2"/> 191 <param name="wire_type" value="0"/> 192 <param name="miss_buffer_assoc" value="0"/> 193 <param name="fetch_buffer_assoc" value="0"/> 194 <param name="prefetch_buffer_assoc" value="0"/> 195 <param name="writeback_buffer_assoc" value="0"/> 196 <param name="miss_buffer_banks" value="1"/> 197 <param name="fetch_buffer_banks" value="1"/> 198 <param name="prefetch_buffer_banks" value="1"/> 199 <param name="writeback_buffer_banks" value="1"/> 200 <param name="cache_access_mode" value="1"/> 201 <param name="miss_buff_access_mode" value="0"/> 202 <param name="fetch_buff_access_mode" value="0"/> 203 <param name="prefetch_buff_access_mode" value="0"/> 204 <param name="writeback_buff_access_mode"value="0"/> 205 <param name="cache_rw_ports" value="1"/> 206 <param name="cache_rd_ports" value="0"/> 207 <param name="cache_wr_ports" value="0"/> 208 <param name="cache_se_rd_ports" value="0"/> 209 <param name="cache_search_ports" value="0"/> 210 <param name="miss_buff_rw_ports" value="1"/> 211 <param name="miss_buff_rd_ports" value="0"/> 212 <param name="miss_buff_wr_ports" value="0"/> 213 <param name="miss_buff_se_rd_ports" value="0"/> 214 <param name="miss_buff_search_ports" value="1"/> 215 <param name="fetch_buff_rw_ports" value="1"/> 216 <param name="fetch_buff_rd_ports" value="0"/> 217 <param name="fetch_buff_wr_ports" value="0"/> 218 <param name="fetch_buff_se_rd_ports" value="0"/> 219 <param name="fetch_buff_search_ports" value="1"/> 220 <param name="pf_buff_rw_ports" value="1"/> 221 <param name="pf_buff_rd_ports" value="0"/> 222 <param name="pf_buff_wr_ports" value="0"/> 223 <param name="pf_buff_se_rd_ports" value="0"/> 224 <param name="pf_buff_search_ports" value="1"/> 225 <param name="wb_buff_rw_ports" value="1"/> 226 <param name="wb_buff_rd_ports" value="0"/> 227 <param name="wb_buff_wr_ports" value="0"/> 228 <param name="wb_buff_se_rd_ports" value="0"/> 229 <param name="wb_buff_search_ports" value="1"/> 230 <param name="pure_ram" value="0"/> 231 <stat name="num_data_array_reads" value="3959"/> 232 <stat name="num_data_array_writes" value="8086"/> 233 <stat name="num_tag_array_reads" value="274"/> 234 <stat name="num_tag_array_writes" value="12046"/> 235 <stat name="read_misses" value="27"/> 236 <stat name="write_misses" value="1204"/> 237 <stat name="conflicts" value="1231"/> 238 <stat name="duty_cycle" value="1"/> 239 </component> 240 </component> 241 </component> 242</component> 243