1<?xml version="1.0" ?>
2<component id="root" name="root">
3	<component id="system" name="system" type="System">
4		<param name="core_tech_node" value="40"/>
5		<param name="target_core_clockrate" value="1700"/>
6		<param name="temperature" value="380"/>
7		<param name="interconnect_projection_type" value="1"/>
8		<param name="device_type" value="0"/>
9		<param name="longer_channel_device" value="0"/>
10		<param name="machine_bits" value="64"/>
11		<param name="virtual_address_width" value="64"/>
12		<param name="physical_address_width" value="36"/>
13		<param name="virtual_memory_page_size" value="4096"/>
14		<param name="wire_is_mat_type" value="2"/>
15		<param name="wire_os_mat_type" value="2"/>
16		<param name="delay_wt" value="100"/>
17		<param name="area_wt" value="0"/>
18		<param name="dynamic_power_wt" value="100"/>
19		<param name="leakage_power_wt" value="0"/>
20		<param name="cycle_time_wt" value="0"/>
21		<param name="delay_dev" value="10000"/>
22		<param name="area_dev" value="10000"/>
23		<param name="dynamic_power_dev" value="10000"/>
24		<param name="leakage_power_dev" value="10000"/>
25		<param name="cycle_time_dev" value="10000"/>
26		<param name="ed" value="2"/>
27		<param name="burst_len" value="1"/>
28		<param name="int_prefetch_w" value="1"/>
29		<param name="page_sz_bits" value="0"/>
30		<param name="rpters_in_htree" value="1"/>
31		<param name="ver_htree_wires_over_array" value="0"/>
32		<param name="nuca" value="0"/>
33		<param name="nuca_bank_count" value="0"/>
34		<param name="force_cache_config" value="0"/>
35		<param name="wt" value="0"/>
36		<param name="force_wiretype" value="0"/>
37		<param name="print_detail" value="1"/>
38		<param name="add_ecc_b_" value="1"/>
39		<param name="broadcast_addr_din_over_ver_htrees" value="0"/>
40		<stat name="total_cycles" value="150"/>
41		<component id="system.core0" name="core0" type="Core">
42			<param name="clock_rate" value="1700"/>
43			<param name="opt_local" value="0"/>
44			<param name="instruction_length" value="32"/>
45			<param name="opcode_width" value="8"/>
46			<param name="x86" value="1"/>
47			<param name="micro_opcode_width" value="8"/>
48			<param name="machine_type" value="0"/>
49			<param name="number_hardware_threads" value="2"/>
50			<param name="fetch_width" value="1"/>
51			<param name="number_instruction_fetch_ports" value="1"/>
52			<param name="decode_width" value="2"/>
53			<param name="issue_width" value="2"/>
54			<param name="peak_issue_width" value="2"/>
55			<param name="commit_width" value="2"/>
56			<param name="fp_issue_width" value="2"/>
57			<param name="prediction_width" value="1"/>
58			<param name="int_pipelines" value="2"/>
59			<param name="fp_pipelines" value="1"/>
60			<param name="int_pipeline_depth" value="12"/>
61			<param name="fp_pipeline_depth" value="13"/>
62			<param name="ALU_per_core" value="2"/>
63			<param name="MUL_per_core" value="1"/>
64			<param name="FPU_per_core" value="1"/>
65			<param name="instruction_buffer_size" value="16"/>
66			<param name="instruction_window_scheme" value="0"/>
67			<param name="instruction_window_size" value="7"/>
68			<param name="fp_instruction_window_size" value="18"/>
69			<param name="ROB_size" value="56"/>
70			<param name="archi_Regs_IRF_size" value="30"/>
71			<param name="archi_Regs_FRF_size" value="48"/>
72			<param name="phy_Regs_IRF_size" value="34"/>
73			<param name="phy_Regs_FRF_size" value="40"/>
74			<param name="rename_scheme" value="0"/>
75			<param name="register_window_size" value="0"/>
76			<param name="register_window_throughput" value="4"/>
77			<param name="register_window_latency" value="4"/>
78			<param name="store_buffer_size" value="32"/>
79			<param name="load_buffer_size" value="22"/>
80			<param name="memory_ports" value="1"/>
81			<param name="RAS_size" value="16"/>
82			<param name="execu_wire_mat_type" value="2"/>
83			<param name="execu_bypass_base_width" value="1"/>
84			<param name="execu_bypass_base_height" value="1"/>
85			<param name="execu_bypass_start_wiring_level"value="3"/>
86			<param name="execu_bypass_route_over_perc" value="1"/>
87			<param name="globalCheckpoint" value="32"/>
88			<param name="perThreadState" value="8"/>
89			<param name="ROB_assoc" value="1"/>
90			<param name="ROB_nbanks" value="1"/>
91			<param name="ROB_tag_width" value="0"/>
92			<param name="scheduler_assoc" value="0"/>
93			<param name="scheduler_nbanks" value="1"/>
94			<param name="register_window_assoc" value="1"/>
95			<param name="register_window_nbanks" value="1"/>
96			<param name="register_window_tag_width" value="0"/>
97			<param name="register_window_rw_ports" value="1"/>
98			<param name="phy_Regs_IRF_assoc" value="1"/>
99			<param name="phy_Regs_IRF_nbanks" value="1"/>
100			<param name="phy_Regs_IRF_tag_width" value="0"/>
101			<param name="phy_Regs_IRF_rd_ports" value="1"/>
102			<param name="phy_Regs_IRF_wr_ports" value="1"/>
103			<param name="phy_Regs_FRF_assoc" value="1"/>
104			<param name="phy_Regs_FRF_nbanks" value="1"/>
105			<param name="phy_Regs_FRF_tag_width" value="0"/>
106			<param name="phy_Regs_FRF_rd_ports" value="1"/>
107			<param name="phy_Regs_FRF_wr_ports" value="1"/>
108			<param name="front_rat_nbanks" value="1"/>
109			<param name="front_rat_rw_ports" value="1"/>
110			<param name="retire_rat_nbanks" value="1"/>
111			<param name="retire_rat_rw_ports" value="0"/>
112			<param name="freelist_nbanks" value="1"/>
113			<param name="freelist_rw_ports" value="1"/>
114			<param name="load_buffer_assoc" value="0"/>
115			<param name="load_buffer_nbanks" value="1"/>
116			<param name="store_buffer_assoc" value="0"/>
117			<param name="store_buffer_nbanks" value="1"/>
118			<param name="instruction_buffer_assoc" value="1"/>
119			<param name="instruction_buffer_nbanks" value="1"/>
120			<param name="instruction_buffer_tag_width" value="0"/>
121			<stat name="total_instructions" value="100"/>
122			<stat name="int_instructions" value="80"/>
123			<stat name="fp_instructions" value="20"/>
124			<stat name="branch_instructions" value="25"/>
125			<stat name="branch_mispredictions" value="2"/>
126			<stat name="load_instructions" value="50"/>
127			<stat name="store_instructions" value="15"/>
128			<stat name="committed_instructions" value="100"/>
129			<stat name="committed_int_instructions" value="80"/>
130			<stat name="committed_fp_instructions" value="20"/>
131			<stat name="pipeline_duty_cycle" value="1"/>
132			<stat name="total_cycles" value="150"/>
133			<stat name="ROB_reads" value="100"/>
134			<stat name="ROB_writes" value="100"/>
135			<stat name="rename_reads" value="100"/>
136			<stat name="rename_writes" value="100"/>
137			<stat name="fp_rename_reads" value="100"/>
138			<stat name="fp_rename_writes" value="100"/>
139			<stat name="inst_window_reads" value="80"/>
140			<stat name="inst_window_writes" value="80"/>
141			<stat name="inst_window_wakeup_accesses" value="80"/>
142			<stat name="fp_inst_window_reads" value="20"/>
143			<stat name="fp_inst_window_writes" value="20"/>
144			<stat name="fp_inst_window_wakeup_accesses" value="20"/>
145			<stat name="int_regfile_reads" value="160"/>
146			<stat name="float_regfile_reads" value="40"/>
147			<stat name="int_regfile_writes" value="80"/>
148			<stat name="float_regfile_writes" value="20"/>
149			<stat name="function_calls" value="0"/>
150			<stat name="context_switches" value="0"/>
151			<stat name="ialu_accesses" value="70"/>
152			<stat name="fpu_accesses" value="20"/>
153			<stat name="mul_accesses" value="10"/>
154			<stat name="cdb_alu_accesses" value="70"/>
155			<stat name="cdb_mul_accesses" value="10"/>
156			<stat name="cdb_fpu_accesses" value="20"/>
157			<stat name="IFU_duty_cycle" value="1"/>
158			<stat name="LSU_duty_cycle" value="1"/>
159			<stat name="MemManU_I_duty_cycle" value="1"/>
160			<stat name="MemManU_D_duty_cycle" value="1"/>
161			<stat name="ALU_duty_cycle" value="1"/>
162			<stat name="MUL_duty_cycle" value="1"/>
163			<stat name="FPU_duty_cycle" value="1"/>
164			<stat name="ALU_cdb_duty_cycle" value="1"/>
165			<stat name="MUL_cdb_duty_cycle" value="1"/>
166			<stat name="FPU_cdb_duty_cycle" value="1"/>
167			<component id="system.core0.predictor" name="PBT" type="BranchPredictor">
168				<param name="assoc" value="1"/>
169				<param name="nbanks" value="1"/>
170				<param name="local_l1_predictor_size" value="12"/>
171				<param name="local_l2_predictor_size" value="4"/>
172				<param name="local_predictor_entries" value="8192"/>
173				<param name="global_predictor_entries" value="8192"/>
174				<param name="global_predictor_bits" value="4"/>
175				<param name="chooser_predictor_entries" value="8192"/>
176				<param name="chooser_predictor_bits" value="4"/>
177			</component>
178			<component id="system.core0.itlb" name="itlb" type="InstructionTLB">
179				<param name="number_entries" value="512"/>
180				<param name="latency" value="8"/>
181				<param name="throughput" value="3"/>
182				<param name="assoc" value="0"/>
183				<param name="nbanks" value="1"/>
184				<stat name="total_accesses" value="50"/>
185				<stat name="total_misses" value="0"/>
186				<stat name="conflicts" value="0"/>
187			</component>
188			<component id="system.core0.icache" name="Instruction Cache" type="CacheUnit">
189				<param name="level" value="1"/>
190				<param name="size" value="32768"/>
191				<param name="block_size" value="64"/>
192				<param name="assoc" value="2"/>
193				<param name="num_banks" value="1"/>
194				<param name="latency" value="8"/>
195				<param name="throughput" value="3"/>
196				<param name="miss_buffer_size" value="2"/>
197				<param name="fetch_buffer_size" value="2"/>
198				<param name="prefetch_buffer_size" value="2"/>
199				<param name="writeback_buffer_size" value="0"/>
200				<param name="clockrate" value="0"/>
201				<param name="tech_type" value="0"/>
202				<param name="Directory_type" value="2"/>
203				<param name="device_type" value="0"/>
204				<param name="core_type" value="1"/>
205				<param name="wire_mat_type" value="2"/>
206				<param name="wire_type" value="0"/>
207				<param name="miss_buffer_assoc" value="0"/>
208				<param name="fetch_buffer_assoc" value="0"/>
209				<param name="prefetch_buffer_assoc" value="0"/>
210				<param name="writeback_buffer_assoc" value="0"/>
211				<param name="miss_buffer_banks" value="1"/>
212				<param name="fetch_buffer_banks" value="1"/>
213				<param name="prefetch_buffer_banks" value="1"/>
214				<param name="writeback_buffer_banks" value="1"/>
215				<param name="cache_access_mode" value="0"/>
216				<param name="miss_buff_access_mode" value="2"/>
217				<param name="fetch_buff_access_mode" value="2"/>
218				<param name="prefetch_buff_access_mode" value="2"/>
219				<param name="writeback_buff_access_mode"value="2"/>
220				<param name="cache_rw_ports" value="1"/>
221				<param name="cache_rd_ports" value="0"/>
222				<param name="cache_wr_ports" value="0"/>
223				<param name="cache_se_rd_ports" value="0"/>
224				<param name="cache_search_ports" value="0"/>
225				<param name="miss_buff_rw_ports" value="1"/>
226				<param name="miss_buff_rd_ports" value="0"/>
227				<param name="miss_buff_wr_ports" value="0"/>
228				<param name="miss_buff_se_rd_ports" value="0"/>
229				<param name="miss_buff_search_ports" value="1"/>
230				<param name="fetch_buff_rw_ports" value="1"/>
231				<param name="fetch_buff_rd_ports" value="0"/>
232				<param name="fetch_buff_wr_ports" value="0"/>
233				<param name="fetch_buff_se_rd_ports" value="0"/>
234				<param name="fetch_buff_search_ports" value="1"/>
235				<param name="pf_buff_rw_ports" value="1"/>
236				<param name="pf_buff_rd_ports" value="0"/>
237				<param name="pf_buff_wr_ports" value="0"/>
238				<param name="pf_buff_se_rd_ports" value="0"/>
239				<param name="pf_buff_search_ports" value="1"/>
240				<param name="wb_buff_rw_ports" value="1"/>
241				<param name="wb_buff_rd_ports" value="0"/>
242				<param name="wb_buff_wr_ports" value="0"/>
243				<param name="wb_buff_se_rd_ports" value="0"/>
244				<param name="wb_buff_search_ports" value="1"/>
245				<param name="pure_ram" value="0"/>
246				<stat name="read_accesses" value="50"/>
247				<stat name="read_misses" value="12"/>
248				<stat name="conflicts" value="1"/>
249				<stat name="duty_cycle" value="1"/>
250			</component>
251			<component id="system.core0.dtlb" name="dtlb" type="DataTLB">
252				<param name="number_entries" value="512"/>
253				<param name="latency" value="8"/>
254				<param name="throughput" value="3"/>
255				<param name="assoc" value="0"/>
256				<param name="nbanks" value="1"/>
257				<stat name="read_accesses" value="65"/>
258				<stat name="read_misses" value="0"/>
259				<stat name="conflicts" value="0"/>
260			</component>
261			<component id="system.core0.dcache" name="Data Cache" type="CacheUnit">
262				<param name="level" value="1"/>
263				<param name="size" value="32768"/>
264				<param name="block_size" value="64"/>
265				<param name="assoc" value="8"/>
266				<param name="num_banks" value="1"/>
267				<param name="latency" value="8"/>
268				<param name="throughput" value="3"/>
269				<param name="miss_buffer_size" value="8"/>
270				<param name="fetch_buffer_size" value="8"/>
271				<param name="prefetch_buffer_size" value="8"/>
272				<param name="writeback_buffer_size" value="8"/>
273				<param name="clockrate" value="0"/>
274				<param name="tech_type" value="0"/>
275				<param name="Directory_type" value="2"/>
276				<param name="device_type" value="0"/>
277				<param name="core_type" value="1"/>
278				<param name="wire_mat_type" value="2"/>
279				<param name="wire_type" value="0"/>
280				<param name="miss_buffer_assoc" value="0"/>
281				<param name="fetch_buffer_assoc" value="0"/>
282				<param name="prefetch_buffer_assoc" value="0"/>
283				<param name="writeback_buffer_assoc" value="0"/>
284				<param name="miss_buffer_banks" value="1"/>
285				<param name="fetch_buffer_banks" value="1"/>
286				<param name="prefetch_buffer_banks" value="1"/>
287				<param name="writeback_buffer_banks" value="1"/>
288				<param name="cache_access_mode" value="0"/>
289				<param name="miss_buff_access_mode" value="2"/>
290				<param name="fetch_buff_access_mode" value="2"/>
291				<param name="prefetch_buff_access_mode" value="2"/>
292				<param name="writeback_buff_access_mode"value="2"/>
293				<param name="cache_rw_ports" value="1"/>
294				<param name="cache_rd_ports" value="0"/>
295				<param name="cache_wr_ports" value="0"/>
296				<param name="cache_se_rd_ports" value="0"/>
297				<param name="cache_search_ports" value="0"/>
298				<param name="miss_buff_rw_ports" value="1"/>
299				<param name="miss_buff_rd_ports" value="0"/>
300				<param name="miss_buff_wr_ports" value="0"/>
301				<param name="miss_buff_se_rd_ports" value="0"/>
302				<param name="miss_buff_search_ports" value="1"/>
303				<param name="fetch_buff_rw_ports" value="1"/>
304				<param name="fetch_buff_rd_ports" value="0"/>
305				<param name="fetch_buff_wr_ports" value="0"/>
306				<param name="fetch_buff_se_rd_ports" value="0"/>
307				<param name="fetch_buff_search_ports" value="1"/>
308				<param name="pf_buff_rw_ports" value="1"/>
309				<param name="pf_buff_rd_ports" value="0"/>
310				<param name="pf_buff_wr_ports" value="0"/>
311				<param name="pf_buff_se_rd_ports" value="0"/>
312				<param name="pf_buff_search_ports" value="1"/>
313				<param name="wb_buff_rw_ports" value="1"/>
314				<param name="wb_buff_rd_ports" value="0"/>
315				<param name="wb_buff_wr_ports" value="0"/>
316				<param name="wb_buff_se_rd_ports" value="0"/>
317				<param name="wb_buff_search_ports" value="1"/>
318				<param name="pure_ram" value="0"/>
319				<stat name="read_accesses" value="50"/>
320				<stat name="write_accesses" value="15"/>
321				<stat name="read_misses" value="12"/>
322				<stat name="write_misses" value="3"/>
323				<stat name="conflicts" value="1"/>
324				<stat name="duty_cycle" value="1"/>
325			</component>
326			<component id="system.core0.btargetbuf" name="btargetbuf" type="BranchTargetBuffer">
327				<param name="size" value="8192"/>
328				<param name="block_size" value="4"/>
329				<param name="assoc" value="2"/>
330				<param name="num_banks" value="1"/>
331				<param name="latency" value="1"/>
332				<param name="throughput" value="3"/>
333				<param name="rw_ports" value="1"/>
334				<stat name="read_accesses" value="25"/>
335				<stat name="write_accesses" value="25"/>
336			</component>
337		</component>
338		<component id="system.L20" name="L2 Cache" type="CacheUnit">
339			<param name="level" value="2"/>
340			<param name="size" value="524288"/>
341			<param name="block_size" value="64"/>
342			<param name="assoc" value="16"/>
343			<param name="num_banks" value="1"/>
344			<param name="latency" value="8"/>
345			<param name="throughput" value="23"/>
346			<param name="miss_buffer_size" value="16"/>
347			<param name="fetch_buffer_size" value="16"/>
348			<param name="prefetch_buffer_size" value="16"/>
349			<param name="writeback_buffer_size" value="16"/>
350			<param name="clockrate" value="1700"/>
351			<param name="tech_type" value="0"/>
352			<param name="Directory_type" value="2"/>
353			<param name="device_type" value="0"/>
354			<param name="core_type" value="1"/>
355			<param name="wire_mat_type" value="2"/>
356			<param name="wire_type" value="0"/>
357			<param name="miss_buffer_assoc" value="0"/>
358			<param name="fetch_buffer_assoc" value="0"/>
359			<param name="prefetch_buffer_assoc" value="0"/>
360			<param name="writeback_buffer_assoc" value="0"/>
361			<param name="miss_buffer_banks" value="1"/>
362			<param name="fetch_buffer_banks" value="1"/>
363			<param name="prefetch_buffer_banks" value="1"/>
364			<param name="writeback_buffer_banks" value="1"/>
365			<param name="cache_access_mode" value="1"/>
366			<param name="miss_buff_access_mode" value="0"/>
367			<param name="fetch_buff_access_mode" value="0"/>
368			<param name="prefetch_buff_access_mode" value="0"/>
369			<param name="writeback_buff_access_mode"value="0"/>
370			<param name="cache_rw_ports" value="1"/>
371			<param name="cache_rd_ports" value="0"/>
372			<param name="cache_wr_ports" value="0"/>
373			<param name="cache_se_rd_ports" value="0"/>
374			<param name="cache_search_ports" value="0"/>
375			<param name="miss_buff_rw_ports" value="1"/>
376			<param name="miss_buff_rd_ports" value="0"/>
377			<param name="miss_buff_wr_ports" value="0"/>
378			<param name="miss_buff_se_rd_ports" value="0"/>
379			<param name="miss_buff_search_ports" value="1"/>
380			<param name="fetch_buff_rw_ports" value="1"/>
381			<param name="fetch_buff_rd_ports" value="0"/>
382			<param name="fetch_buff_wr_ports" value="0"/>
383			<param name="fetch_buff_se_rd_ports" value="0"/>
384			<param name="fetch_buff_search_ports" value="1"/>
385			<param name="pf_buff_rw_ports" value="1"/>
386			<param name="pf_buff_rd_ports" value="0"/>
387			<param name="pf_buff_wr_ports" value="0"/>
388			<param name="pf_buff_se_rd_ports" value="0"/>
389			<param name="pf_buff_search_ports" value="1"/>
390			<param name="wb_buff_rw_ports" value="1"/>
391			<param name="wb_buff_rd_ports" value="0"/>
392			<param name="wb_buff_wr_ports" value="0"/>
393			<param name="wb_buff_se_rd_ports" value="0"/>
394			<param name="wb_buff_search_ports" value="1"/>
395			<param name="pure_ram" value="0"/>
396			<stat name="read_accesses" value="15"/>
397			<stat name="write_accesses" value="5"/>
398			<stat name="read_misses" value="3"/>
399			<stat name="write_misses" value="1"/>
400			<stat name="conflicts" value="1"/>
401			<stat name="duty_cycle" value="1.0"/>
402		</component>
403	</component>
404</component>
405