110234Syasuko.eckert@amd.com/***************************************************************************** 210234Syasuko.eckert@amd.com * McPAT 310234Syasuko.eckert@amd.com * SOFTWARE LICENSE AGREEMENT 410234Syasuko.eckert@amd.com * Copyright (c) 2010-2013 Advanced Micro Devices, Inc. 510234Syasuko.eckert@amd.com * All Rights Reserved 610234Syasuko.eckert@amd.com * 710234Syasuko.eckert@amd.com * Redistribution and use in source and binary forms, with or without 810234Syasuko.eckert@amd.com * modification, are permitted provided that the following conditions are 910234Syasuko.eckert@amd.com * met: redistributions of source code must retain the above copyright 1010234Syasuko.eckert@amd.com * notice, this list of conditions and the following disclaimer; 1110234Syasuko.eckert@amd.com * redistributions in binary form must reproduce the above copyright 1210234Syasuko.eckert@amd.com * notice, this list of conditions and the following disclaimer in the 1310234Syasuko.eckert@amd.com * documentation and/or other materials provided with the distribution; 1410234Syasuko.eckert@amd.com * neither the name of the copyright holders nor the names of its 1510234Syasuko.eckert@amd.com * contributors may be used to endorse or promote products derived from 1610234Syasuko.eckert@amd.com * this software without specific prior written permission. 1710234Syasuko.eckert@amd.com 1810234Syasuko.eckert@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1910234Syasuko.eckert@amd.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2010234Syasuko.eckert@amd.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2110234Syasuko.eckert@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2210234Syasuko.eckert@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2310234Syasuko.eckert@amd.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2410234Syasuko.eckert@amd.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2510234Syasuko.eckert@amd.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2610234Syasuko.eckert@amd.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2710234Syasuko.eckert@amd.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2810234Syasuko.eckert@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2910234Syasuko.eckert@amd.com * 3010234Syasuko.eckert@amd.com * Author: Joel Hestness 3110234Syasuko.eckert@amd.com * 3210234Syasuko.eckert@amd.com ***************************************************************************/ 3310234Syasuko.eckert@amd.com 3410234Syasuko.eckert@amd.com#ifndef BUS_INTERCONNECT_H_ 3510234Syasuko.eckert@amd.com#define BUS_INTERCONNECT_H_ 3610234Syasuko.eckert@amd.com 3710234Syasuko.eckert@amd.com#include "array.h" 3810234Syasuko.eckert@amd.com#include "basic_components.h" 3910234Syasuko.eckert@amd.com#include "interconnect.h" 4010234Syasuko.eckert@amd.com#include "logic.h" 4110234Syasuko.eckert@amd.com#include "parameter.h" 4210234Syasuko.eckert@amd.com 4310234Syasuko.eckert@amd.comclass BusInterconnectParameters { 4410234Syasuko.eckert@amd.compublic: 4510234Syasuko.eckert@amd.com double clockRate; 4610234Syasuko.eckert@amd.com int flit_size; 4710234Syasuko.eckert@amd.com int input_ports; 4810234Syasuko.eckert@amd.com int output_ports; 4910234Syasuko.eckert@amd.com int min_ports; 5010234Syasuko.eckert@amd.com int global_linked_ports; 5110234Syasuko.eckert@amd.com int virtual_channel_per_port; 5210234Syasuko.eckert@amd.com int input_buffer_entries_per_vc; 5310234Syasuko.eckert@amd.com int total_nodes; 5410234Syasuko.eckert@amd.com double link_throughput; 5510234Syasuko.eckert@amd.com double link_latency; 5610234Syasuko.eckert@amd.com double chip_coverage; 5710234Syasuko.eckert@amd.com bool pipelinable; 5810234Syasuko.eckert@amd.com double route_over_perc; 5910234Syasuko.eckert@amd.com bool has_global_link; 6010234Syasuko.eckert@amd.com bool type; 6110234Syasuko.eckert@amd.com double M_traffic_pattern; 6210234Syasuko.eckert@amd.com double link_base_width; 6310234Syasuko.eckert@amd.com double link_base_height; 6410234Syasuko.eckert@amd.com int link_start_wiring_level; 6510234Syasuko.eckert@amd.com}; 6610234Syasuko.eckert@amd.com 6710234Syasuko.eckert@amd.comclass BusInterconnectStatistics { 6810234Syasuko.eckert@amd.compublic: 6910234Syasuko.eckert@amd.com double duty_cycle; 7010234Syasuko.eckert@amd.com double total_access; 7110234Syasuko.eckert@amd.com}; 7210234Syasuko.eckert@amd.com 7310234Syasuko.eckert@amd.comclass BusInterconnect : public McPATComponent { 7410234Syasuko.eckert@amd.compublic: 7510234Syasuko.eckert@amd.com Interconnect* link_bus; 7610234Syasuko.eckert@amd.com 7710234Syasuko.eckert@amd.com int ithNoC; 7810234Syasuko.eckert@amd.com InputParameter interface_ip; 7910234Syasuko.eckert@amd.com double link_len; 8010234Syasuko.eckert@amd.com double scktRatio, chip_PR_overhead, macro_PR_overhead; 8110234Syasuko.eckert@amd.com BusInterconnectParameters bus_params; 8210234Syasuko.eckert@amd.com BusInterconnectStatistics bus_stats; 8310234Syasuko.eckert@amd.com uca_org_t local_result; 8410234Syasuko.eckert@amd.com statsDef stats_t; 8510234Syasuko.eckert@amd.com double M_traffic_pattern; 8610234Syasuko.eckert@amd.com 8710234Syasuko.eckert@amd.com BusInterconnect(XMLNode* _xml_data, InputParameter* interface_ip_); 8810234Syasuko.eckert@amd.com void set_param_stats(); 8910234Syasuko.eckert@amd.com void set_duty_cycle(double duty_cycle); 9010234Syasuko.eckert@amd.com void set_number_of_accesses(double total_accesses); 9110234Syasuko.eckert@amd.com void computeEnergy(); 9210234Syasuko.eckert@amd.com ~BusInterconnect(); 9310234Syasuko.eckert@amd.com}; 9410234Syasuko.eckert@amd.com 9510234Syasuko.eckert@amd.com#endif /* BUS_INTERCONNECT_H_ */ 96