1/*****************************************************************************
2 *                                McPAT
3 *                      SOFTWARE LICENSE AGREEMENT
4 *            Copyright (c) 2010-2013 Advanced Micro Devices, Inc.
5 *                          All Rights Reserved
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are
9 * met: redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer;
11 * redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution;
14 * neither the name of the copyright holders nor the names of its
15 * contributors may be used to endorse or promote products derived from
16 * this software without specific prior written permission.
17
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 *
30 * Author: Joel Hestness
31 *
32 ***************************************************************************/
33
34#ifndef BUS_INTERCONNECT_H_
35#define BUS_INTERCONNECT_H_
36
37#include "array.h"
38#include "basic_components.h"
39#include "interconnect.h"
40#include "logic.h"
41#include "parameter.h"
42
43class BusInterconnectParameters {
44public:
45    double clockRate;
46    int flit_size;
47    int input_ports;
48    int output_ports;
49    int min_ports;
50    int global_linked_ports;
51    int virtual_channel_per_port;
52    int input_buffer_entries_per_vc;
53    int total_nodes;
54    double link_throughput;
55    double link_latency;
56    double chip_coverage;
57    bool pipelinable;
58    double route_over_perc;
59    bool has_global_link;
60    bool type;
61    double M_traffic_pattern;
62    double link_base_width;
63    double link_base_height;
64    int link_start_wiring_level;
65};
66
67class BusInterconnectStatistics {
68public:
69    double duty_cycle;
70    double total_access;
71};
72
73class BusInterconnect : public McPATComponent {
74public:
75    Interconnect* link_bus;
76
77    int ithNoC;
78    InputParameter interface_ip;
79    double link_len;
80    double scktRatio, chip_PR_overhead, macro_PR_overhead;
81    BusInterconnectParameters bus_params;
82    BusInterconnectStatistics bus_stats;
83    uca_org_t local_result;
84    statsDef stats_t;
85    double M_traffic_pattern;
86
87    BusInterconnect(XMLNode* _xml_data, InputParameter* interface_ip_);
88    void set_param_stats();
89    void set_duty_cycle(double duty_cycle);
90    void set_number_of_accesses(double total_accesses);
91    void computeEnergy();
92    ~BusInterconnect();
93};
94
95#endif /* BUS_INTERCONNECT_H_ */
96