TG11LVT.model revision 10447
110447Snilay@cs.wisc.edu# WARNING: Most commercial fabs will not be happy if you release their exact 210447Snilay@cs.wisc.edu# process information! If you derive these numbers through SPICE models, 310447Snilay@cs.wisc.edu# the process design kit, or any other confidential material, please round-off 410447Snilay@cs.wisc.edu# the values and leave the process name unidentifiable by fab (i.e. call it 510447Snilay@cs.wisc.edu# Bulk90LVT instead of TSMC90LVT) if you release parameters publicly. This 610447Snilay@cs.wisc.edu# rule may not apply for open processes, but you may want to check. 710447Snilay@cs.wisc.edu 810447Snilay@cs.wisc.edu# All units are in SI, (volts, meters, kelvin, farads, ohms, amps, etc.) 910447Snilay@cs.wisc.edu 1010447Snilay@cs.wisc.edu# This file contains the model for a Tri-Gate (Multi-Gate) 11nm LVT process 1110447Snilay@cs.wisc.eduName = TG11LVT 1210447Snilay@cs.wisc.edu 1310447Snilay@cs.wisc.edu# Supply voltage used in the circuit and for characterizations (V) 1410447Snilay@cs.wisc.eduVdd = 0.6 1510447Snilay@cs.wisc.edu# Temperature (K) 1610447Snilay@cs.wisc.eduTemperature = 340 1710447Snilay@cs.wisc.edu 1810447Snilay@cs.wisc.edu# ============================================================================= 1910447Snilay@cs.wisc.edu# Parameters for transistors 2010447Snilay@cs.wisc.edu# ============================================================================= 2110447Snilay@cs.wisc.edu 2210447Snilay@cs.wisc.edu# Contacted gate pitch (m) 2310447Snilay@cs.wisc.eduGate->PitchContacted = 0.080e-6 2410447Snilay@cs.wisc.edu 2510447Snilay@cs.wisc.edu# Min gate width (m) 2610447Snilay@cs.wisc.eduGate->MinWidth = 0.080e-6 2710447Snilay@cs.wisc.edu 2810447Snilay@cs.wisc.edu# Gate cap per unit width (F/m) 2910447Snilay@cs.wisc.eduGate->CapPerWidth = 0.61e-9 3010447Snilay@cs.wisc.edu# Source/Drain cap per unit width (F/m) 3110447Snilay@cs.wisc.eduDrain->CapPerWidth = 0.56e-9 3210447Snilay@cs.wisc.edu 3310447Snilay@cs.wisc.edu# Parameters characterization temperature (K) 3410447Snilay@cs.wisc.eduNmos->CharacterizedTemperature = 300.0 3510447Snilay@cs.wisc.eduPmos->CharacterizedTemperature = 300.0 3610447Snilay@cs.wisc.edu 3710447Snilay@cs.wisc.edu#------------------------------------------------------------------------------ 3810447Snilay@cs.wisc.edu# I_Eff definition in Na, IEDM 2002 3910447Snilay@cs.wisc.edu# I_EFF = (I(VG = 0.5, VD = 1.0) + I(VG = 1.0, VD = 0.5))/2 4010447Snilay@cs.wisc.edu# R_EFF = VDD / I_EFF * 1 / (2 ln(2)) 4110447Snilay@cs.wisc.edu# This is generally more accurate for when the delay is input transition time 4210447Snilay@cs.wisc.edu# limited 4310447Snilay@cs.wisc.edu#------------------------------------------------------------------------------ 4410447Snilay@cs.wisc.edu# Effective resistance (Ohm-m) 4510447Snilay@cs.wisc.eduNmos->EffResWidth = 1.16e-3 4610447Snilay@cs.wisc.eduPmos->EffResWidth = 1.28e-3 4710447Snilay@cs.wisc.edu 4810447Snilay@cs.wisc.edu#------------------------------------------------------------------------------ 4910447Snilay@cs.wisc.edu# The ratio of extra effective resistance with each additional stacked 5010447Snilay@cs.wisc.edu# transistor 5110447Snilay@cs.wisc.edu# EffResStackRatio = (R_EFF_NAND2 - R_EFF_INV) / R_EFF_INV) 5210447Snilay@cs.wisc.edu# For example, inverter has an normalized effective drive resistance of 1.0. 5310447Snilay@cs.wisc.edu# A NAND2 (2-stack) will have an effective drive of 1.0 + 0.7, a NAND3 (3-stack) 5410447Snilay@cs.wisc.edu# will have an effective drive of 1.0 + 2 * 0.7. Use NORs for Pmos. This fit 5510447Snilay@cs.wisc.edu# works relatively well up to 4 stacks. This value will change depending on the 5610447Snilay@cs.wisc.edu# VDD used. 5710447Snilay@cs.wisc.edu#------------------------------------------------------------------------------ 5810447Snilay@cs.wisc.edu# Effective resistance stack ratio 5910447Snilay@cs.wisc.eduNmos->EffResStackRatio = 0.89 6010447Snilay@cs.wisc.eduPmos->EffResStackRatio = 0.86 6110447Snilay@cs.wisc.edu 6210447Snilay@cs.wisc.edu#------------------------------------------------------------------------------ 6310447Snilay@cs.wisc.edu# I_OFF defined as |I_DS| for |V_DS| = V_DD and |V_GS| = 0.0 6410447Snilay@cs.wisc.edu# Minimum off current is used in technologies where I_OFF stops scaling 6510447Snilay@cs.wisc.edu# with transistor width below some threshold 6610447Snilay@cs.wisc.edu#------------------------------------------------------------------------------ 6710447Snilay@cs.wisc.edu# Off current per width (A/m) 6810447Snilay@cs.wisc.eduNmos->OffCurrent = 100.0e-3 6910447Snilay@cs.wisc.eduPmos->OffCurrent = 100.0e-3 7010447Snilay@cs.wisc.edu# Minimum off current (A) 7110447Snilay@cs.wisc.eduNmos->MinOffCurrent = 40e-9 7210447Snilay@cs.wisc.eduPmos->MinOffCurrent = 4e-9 7310447Snilay@cs.wisc.edu 7410447Snilay@cs.wisc.edu# Subthreshold swing (V/dec) 7510447Snilay@cs.wisc.eduNmos->SubthresholdSwing = 0.080 7610447Snilay@cs.wisc.eduPmos->SubthresholdSwing = 0.080 7710447Snilay@cs.wisc.edu# DIBL factor (V/V) 7810447Snilay@cs.wisc.eduNmos->DIBL = 0.125 7910447Snilay@cs.wisc.eduPmos->DIBL = 0.125 8010447Snilay@cs.wisc.edu# Subthreshold temperature swing (K/dec) 8110447Snilay@cs.wisc.eduNmos->SubthresholdTempSwing = 100.0 8210447Snilay@cs.wisc.eduPmos->SubthresholdTempSwing = 100.0 8310447Snilay@cs.wisc.edu#------------------------------------------------------------------------------ 8410447Snilay@cs.wisc.edu 8510447Snilay@cs.wisc.edu# ============================================================================= 8610447Snilay@cs.wisc.edu# Parameters for interconnect 8710447Snilay@cs.wisc.edu# ============================================================================= 8810447Snilay@cs.wisc.edu 8910447Snilay@cs.wisc.eduWire->AvailableLayers = [Metal1,Local,Intermediate,Semiglobal,Global] 9010447Snilay@cs.wisc.edu 9110447Snilay@cs.wisc.edu# Metal 1 Wire (used for std cell routing only) 9210447Snilay@cs.wisc.edu# Min width (m) 9310447Snilay@cs.wisc.eduWire->Metal1->MinWidth = 20e-9 9410447Snilay@cs.wisc.edu# Min spacing (m) 9510447Snilay@cs.wisc.eduWire->Metal1->MinSpacing = 20e-9 9610447Snilay@cs.wisc.edu# Resistivity (Ohm-m) 9710447Snilay@cs.wisc.eduWire->Metal1->Resistivity = 6.8e-8 9810447Snilay@cs.wisc.edu# Metal thickness (m) 9910447Snilay@cs.wisc.eduWire->Metal1->MetalThickness = 35.0e-9 10010447Snilay@cs.wisc.edu# Dielectric thickness (m) 10110447Snilay@cs.wisc.eduWire->Metal1->DielectricThickness = 35.0e-9 10210447Snilay@cs.wisc.edu# Dielectric constant 10310447Snilay@cs.wisc.eduWire->Metal1->DielectricConstant = 3.00 10410447Snilay@cs.wisc.edu 10510447Snilay@cs.wisc.edu# Local wire, 1.0X of the M1 pitch 10610447Snilay@cs.wisc.edu# Min width (m) 10710447Snilay@cs.wisc.eduWire->Local->MinWidth = 20e-9 10810447Snilay@cs.wisc.edu# Min spacing (m) 10910447Snilay@cs.wisc.eduWire->Local->MinSpacing = 20e-9 11010447Snilay@cs.wisc.edu# Resistivity (Ohm-m) 11110447Snilay@cs.wisc.eduWire->Local->Resistivity = 6.8e-8 11210447Snilay@cs.wisc.edu# Metal thickness (m) 11310447Snilay@cs.wisc.eduWire->Local->MetalThickness = 35.0e-9 11410447Snilay@cs.wisc.edu# Dielectric thickness (m) 11510447Snilay@cs.wisc.eduWire->Local->DielectricThickness = 35.0e-9 11610447Snilay@cs.wisc.edu# Dielectric constant 11710447Snilay@cs.wisc.eduWire->Local->DielectricConstant = 3.00 11810447Snilay@cs.wisc.edu 11910447Snilay@cs.wisc.edu# Intermediate wire, 2.0X the M1 pitch 12010447Snilay@cs.wisc.edu# Min width (m) 12110447Snilay@cs.wisc.eduWire->Intermediate->MinWidth = 40e-9 12210447Snilay@cs.wisc.edu# Min spacing (m) 12310447Snilay@cs.wisc.eduWire->Intermediate->MinSpacing = 40e-9 12410447Snilay@cs.wisc.edu# Resistivity (Ohm-m) 12510447Snilay@cs.wisc.eduWire->Intermediate->Resistivity = 4.50e-8 12610447Snilay@cs.wisc.edu# Metal thickness (m) 12710447Snilay@cs.wisc.eduWire->Intermediate->MetalThickness = 70.0e-9 12810447Snilay@cs.wisc.edu# Dielectric thickness (m) 12910447Snilay@cs.wisc.eduWire->Intermediate->DielectricThickness = 70.0e-9 13010447Snilay@cs.wisc.edu# Dielectric constant 13110447Snilay@cs.wisc.eduWire->Intermediate->DielectricConstant = 2.80 13210447Snilay@cs.wisc.edu 13310447Snilay@cs.wisc.edu# Semiglobal wire, 4.0X the M1 pitch 13410447Snilay@cs.wisc.edu# Min width (m) 13510447Snilay@cs.wisc.eduWire->Semiglobal->MinWidth = 80e-9 13610447Snilay@cs.wisc.edu# Min spacing (m) 13710447Snilay@cs.wisc.eduWire->Semiglobal->MinSpacing = 80e-9 13810447Snilay@cs.wisc.edu# Resistivity (Ohm-m) 13910447Snilay@cs.wisc.eduWire->Semiglobal->Resistivity = 2.80e-8 14010447Snilay@cs.wisc.edu# Metal thickness (m) 14110447Snilay@cs.wisc.eduWire->Semiglobal->MetalThickness = 150.0e-9 14210447Snilay@cs.wisc.edu# Dielectric thickness (m) 14310447Snilay@cs.wisc.eduWire->Semiglobal->DielectricThickness = 150.0e-9 14410447Snilay@cs.wisc.edu# Dielectric constant 14510447Snilay@cs.wisc.eduWire->Semiglobal->DielectricConstant = 2.60 14610447Snilay@cs.wisc.edu 14710447Snilay@cs.wisc.edu# Global wire, 8.0X the M1 pitch 14810447Snilay@cs.wisc.edu# Min width (m) 14910447Snilay@cs.wisc.eduWire->Global->MinWidth = 160e-9 15010447Snilay@cs.wisc.edu# Min spacing (m) 15110447Snilay@cs.wisc.eduWire->Global->MinSpacing = 160e-9 15210447Snilay@cs.wisc.edu# Resistivity (Ohm-m) 15310447Snilay@cs.wisc.eduWire->Global->Resistivity = 2.30e-8 15410447Snilay@cs.wisc.edu# Metal thickness (m) 15510447Snilay@cs.wisc.eduWire->Global->MetalThickness = 280e-9 15610447Snilay@cs.wisc.edu# Dielectric thickness (m) 15710447Snilay@cs.wisc.eduWire->Global->DielectricThickness = 250e-9 15810447Snilay@cs.wisc.edu# Dielectric constant 15910447Snilay@cs.wisc.eduWire->Global->DielectricConstant = 2.60 16010447Snilay@cs.wisc.edu 16110447Snilay@cs.wisc.edu# ============================================================================= 16210447Snilay@cs.wisc.edu# Parameters for Standard Cells 16310447Snilay@cs.wisc.edu# ============================================================================= 16410447Snilay@cs.wisc.edu 16510447Snilay@cs.wisc.edu# The height of the standard cell is usually a multiple of the vertical 16610447Snilay@cs.wisc.edu# M1 pitch (tracks). By definition, an X1 size cell has transistors 16710447Snilay@cs.wisc.edu# that fit exactly in the given cell height without folding, or leaving 16810447Snilay@cs.wisc.edu# any wasted vertical area 16910447Snilay@cs.wisc.edu 17010447Snilay@cs.wisc.edu# Reasonable values for the number of M1 tracks that we have seen are 8-14 17110447Snilay@cs.wisc.eduStdCell->Tracks = 11 17210447Snilay@cs.wisc.edu# Height overhead due to supply rails, well spacing, etc. Note that this will grow 17310447Snilay@cs.wisc.edu# if the height of the standard cell decreases! 17410447Snilay@cs.wisc.eduStdCell->HeightOverheadFactor = 1.400 17510447Snilay@cs.wisc.edu 17610447Snilay@cs.wisc.edu# Sets the available sizes of each standard cell. Keep in mind that 17710447Snilay@cs.wisc.edu# 1.0 is the biggest cell without any transistor folding 17810447Snilay@cs.wisc.eduStdCell->AvailableSizes = [1.0, 1.4, 2.0, 3.0, 4.0, 6.0, 8.0, 10.0, 12.0, 16.0] 17910447Snilay@cs.wisc.edu 18010447Snilay@cs.wisc.edu 18110447Snilay@cs.wisc.edu 182