two_level.py revision 11154
12817Sksewell@umich.edu# -*- coding: utf-8 -*- 22817Sksewell@umich.edu# Copyright (c) 2015 Jason Power 32817Sksewell@umich.edu# All rights reserved. 42817Sksewell@umich.edu# 52817Sksewell@umich.edu# Redistribution and use in source and binary forms, with or without 62817Sksewell@umich.edu# modification, are permitted provided that the following conditions are 72817Sksewell@umich.edu# met: redistributions of source code must retain the above copyright 82817Sksewell@umich.edu# notice, this list of conditions and the following disclaimer; 92817Sksewell@umich.edu# redistributions in binary form must reproduce the above copyright 102817Sksewell@umich.edu# notice, this list of conditions and the following disclaimer in the 112817Sksewell@umich.edu# documentation and/or other materials provided with the distribution; 122817Sksewell@umich.edu# neither the name of the copyright holders nor the names of its 132817Sksewell@umich.edu# contributors may be used to endorse or promote products derived from 142817Sksewell@umich.edu# this software without specific prior written permission. 152817Sksewell@umich.edu# 162817Sksewell@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172817Sksewell@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182817Sksewell@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192817Sksewell@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202817Sksewell@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212817Sksewell@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222817Sksewell@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232817Sksewell@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242817Sksewell@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252817Sksewell@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262817Sksewell@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272817Sksewell@umich.edu# 282817Sksewell@umich.edu# Authors: Jason Power 294202Sbinkertn@umich.edu 302817Sksewell@umich.edu""" This file creates a single CPU and a two-level cache system. 312817Sksewell@umich.eduThis script takes a single parameter which specifies a binary to execute. 322817Sksewell@umich.eduIf none is provided it executes 'hello' by default (mostly used for testing) 334202Sbinkertn@umich.edu 342817Sksewell@umich.eduSee Part 1, Chapter 3: Adding cache to the configuration script in the 354202Sbinkertn@umich.edulearning_gem5 book for more information about this script. 364486Sbinkertn@umich.eduThis file exports options for the L1 I/D and L2 cache sizes. 374486Sbinkertn@umich.edu 384486Sbinkertn@umich.eduIMPORTANT: If you modify this file, it's likely that the Learning gem5 book 394486Sbinkertn@umich.edu also needs to be updated. For now, email Jason <power.jg@gmail.com> 404202Sbinkertn@umich.edu 414202Sbinkertn@umich.edu""" 424202Sbinkertn@umich.edu 439341SAndreas.Sandberg@arm.com# import the m5 (gem5) library created when gem5 is built 444202Sbinkertn@umich.eduimport m5 455597Sgblack@eecs.umich.edu# import all of the SimObjects 464202Sbinkertn@umich.edufrom m5.objects import * 474202Sbinkertn@umich.edu 484202Sbinkertn@umich.edu# Add the common scripts to our path 494202Sbinkertn@umich.edum5.util.addToPath('../../common') 504202Sbinkertn@umich.edu 514202Sbinkertn@umich.edu# import the caches which we made 524202Sbinkertn@umich.edufrom caches import * 534202Sbinkertn@umich.edu 549919Ssteve.reinhardt@amd.com# import the SimpleOpts module 554202Sbinkertn@umich.eduimport SimpleOpts 564202Sbinkertn@umich.edu 574202Sbinkertn@umich.edu# Set the usage message to display 584202Sbinkertn@umich.eduSimpleOpts.set_usage("usage: %prog [options] <binary to execute>") 594202Sbinkertn@umich.edu 605597Sgblack@eecs.umich.edu# Finalize the arguments and grab the opts so we can pass it on to our objects 612817Sksewell@umich.edu(opts, args) = SimpleOpts.parse_args() 6210426Smitch.hayenga@arm.com 6310426Smitch.hayenga@arm.com# get ISA for the default binary to run. This is mostly for simple testing 6410426Smitch.hayenga@arm.comisa = str(m5.defines.buildEnv['TARGET_ISA']).lower() 658335Snate@binkert.org 668335Snate@binkert.org# Default to running 'hello', use the compiled ISA to find the binary 678335Snate@binkert.orgbinary = 'tests/test-progs/hello/bin/' + isa + '/linux/hello' 688335Snate@binkert.org 698335Snate@binkert.org# Check if there was a binary passed in via the command line and error if 708335Snate@binkert.org# there are too many arguments 718335Snate@binkert.orgif len(args) == 1: 728335Snate@binkert.org binary = args[0] 738335Snate@binkert.orgelif len(args) > 1: 745192Ssaidi@eecs.umich.edu SimpleOpts.print_help() 755192Ssaidi@eecs.umich.edu m5.fatal("Expected a binary to execute as positional argument") 765192Ssaidi@eecs.umich.edu 775192Ssaidi@eecs.umich.edu# create the system we are going to simulate 785192Ssaidi@eecs.umich.edusystem = System() 798887Sgeoffrey.blake@arm.com 809340SAndreas.Sandberg@arm.com# Set the clock fequency of the system (and all of its children) 81system.clk_domain = SrcClockDomain() 82system.clk_domain.clock = '1GHz' 83system.clk_domain.voltage_domain = VoltageDomain() 84 85# Set up the system 86system.mem_mode = 'timing' # Use timing accesses 87system.mem_ranges = [AddrRange('512MB')] # Create an address range 88 89# Create a simple CPU 90system.cpu = TimingSimpleCPU() 91 92# Create an L1 instruction and data cache 93system.cpu.icache = L1ICache(opts) 94system.cpu.dcache = L1DCache(opts) 95 96# Connect the instruction and data caches to the CPU 97system.cpu.icache.connectCPU(system.cpu) 98system.cpu.dcache.connectCPU(system.cpu) 99 100# Create a memory bus, a coherent crossbar, in this case 101system.l2bus = L2XBar() 102 103# Hook the CPU ports up to the l2bus 104system.cpu.icache.connectBus(system.l2bus) 105system.cpu.dcache.connectBus(system.l2bus) 106 107# Create an L2 cache and connect it to the l2bus 108system.l2cache = L2Cache(opts) 109system.l2cache.connectCPUSideBus(system.l2bus) 110 111# Create a memory bus 112system.membus = SystemXBar() 113 114# Connect the L2 cache to the membus 115system.l2cache.connectMemSideBus(system.membus) 116 117# create the interrupt controller for the CPU 118system.cpu.createInterruptController() 119 120# For x86 only, make sure the interrupts are connected to the memory 121# Note: these are directly connected to the memory bus and are not cached 122if m5.defines.buildEnv['TARGET_ISA'] == "x86": 123 system.cpu.interrupts[0].pio = system.membus.master 124 system.cpu.interrupts[0].int_master = system.membus.slave 125 system.cpu.interrupts[0].int_slave = system.membus.master 126 127# Connect the system up to the membus 128system.system_port = system.membus.slave 129 130# Create a DDR3 memory controller 131system.mem_ctrl = DDR3_1600_x64() 132system.mem_ctrl.range = system.mem_ranges[0] 133system.mem_ctrl.port = system.membus.master 134 135# Create a process for a simple "Hello World" application 136process = LiveProcess() 137# Set the command 138# cmd is a list which begins with the executable (like argv) 139process.cmd = [binary] 140# Set the cpu to use the process as its workload and create thread contexts 141system.cpu.workload = process 142system.cpu.createThreads() 143 144# set up the root SimObject and start the simulation 145root = Root(full_system = False, system = system) 146# instantiate all of the objects we've created above 147m5.instantiate() 148 149print "Beginning simulation!" 150exit_event = m5.simulate() 151print 'Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause()) 152