se.py revision 3448
13005Sstever@eecs.umich.edu# Copyright (c) 2006 The Regents of The University of Michigan 23005Sstever@eecs.umich.edu# All rights reserved. 33005Sstever@eecs.umich.edu# 43005Sstever@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 53005Sstever@eecs.umich.edu# modification, are permitted provided that the following conditions are 63005Sstever@eecs.umich.edu# met: redistributions of source code must retain the above copyright 73005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 83005Sstever@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 93005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 103005Sstever@eecs.umich.edu# documentation and/or other materials provided with the distribution; 113005Sstever@eecs.umich.edu# neither the name of the copyright holders nor the names of its 123005Sstever@eecs.umich.edu# contributors may be used to endorse or promote products derived from 133005Sstever@eecs.umich.edu# this software without specific prior written permission. 143005Sstever@eecs.umich.edu# 153005Sstever@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 163005Sstever@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 173005Sstever@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 183005Sstever@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 193005Sstever@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 203005Sstever@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 213005Sstever@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 223005Sstever@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 233005Sstever@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 243005Sstever@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 253005Sstever@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 263005Sstever@eecs.umich.edu# 273005Sstever@eecs.umich.edu# Authors: Steve Reinhardt 283005Sstever@eecs.umich.edu 292710SN/A# Simple test script 302710SN/A# 313005Sstever@eecs.umich.edu# "m5 test.py" 322889SN/A 332667SN/Aimport m5 343005Sstever@eecs.umich.edufrom m5.objects import * 352856SN/Aimport os, optparse, sys 362917SN/Am5.AddToPath('../common') 373395Shsul@eecs.umich.eduimport Simulation 383448Shsul@eecs.umich.edufrom Caches import * 392424SN/A 403444Sktlim@umich.edu# Get paths we might need. It's expected this file is in m5/configs/example. 413444Sktlim@umich.educonfig_path = os.path.dirname(os.path.abspath(__file__)) 423444Sktlim@umich.educonfig_root = os.path.dirname(config_path) 433444Sktlim@umich.edum5_root = os.path.dirname(config_root) 443448Shsul@eecs.umich.eduprint m5_root 453448Shsul@eecs.umich.eduprint config_path 463448Shsul@eecs.umich.eduprint config_root 473448Shsul@eecs.umich.edu 483444Sktlim@umich.edu 492957SN/Aparser = optparse.OptionParser() 502957SN/A 513323Shsul@eecs.umich.edu# Benchmark options 523005Sstever@eecs.umich.eduparser.add_option("-c", "--cmd", 533444Sktlim@umich.edu default=os.path.join(m5_root, "tests/test-progs/hello/bin/alpha/linux/hello"), 542957SN/A help="The binary to run in syscall emulation mode.") 552957SN/Aparser.add_option("-o", "--options", default="", 562957SN/A help="The options to pass to the binary, use \" \" around the entire\ 572957SN/A string.") 582957SN/Aparser.add_option("-i", "--input", default="", 592957SN/A help="A file of input to give to the binary.") 603323Shsul@eecs.umich.edu 613444Sktlim@umich.eduexecfile(os.path.join(config_root, "common", "Options.py")) 622957SN/A 632957SN/A(options, args) = parser.parse_args() 642957SN/A 652957SN/Aif args: 662957SN/A print "Error: script doesn't take any positional arguments" 672957SN/A sys.exit(1) 682957SN/A 692715SN/Aprocess = LiveProcess() 703005Sstever@eecs.umich.eduprocess.executable = options.cmd 712801SN/Aprocess.cmd = options.cmd + " " + options.options 722801SN/Aif options.input != "": 732801SN/A process.input = options.input 742418SN/A 752917SN/Aif options.detailed: 762833SN/A #check for SMT workload 772833SN/A workloads = options.cmd.split(';') 782833SN/A if len(workloads) > 1: 792833SN/A process = [] 802833SN/A smt_idx = 0 812833SN/A inputs = [] 822833SN/A 832833SN/A if options.input != "": 842833SN/A inputs = options.input.split(';') 852833SN/A 862833SN/A for wrkld in workloads: 872833SN/A smt_process = LiveProcess() 883005Sstever@eecs.umich.edu smt_process.executable = wrkld 892833SN/A smt_process.cmd = wrkld + " " + options.options 902833SN/A if inputs and inputs[smt_idx]: 912833SN/A smt_process.input = inputs[smt_idx] 922833SN/A process += [smt_process, ] 932833SN/A smt_idx += 1 942833SN/A 952957SN/A 962957SN/Aif options.timing: 973395Shsul@eecs.umich.edu CPUClass = TimingSimpleCPU 983395Shsul@eecs.umich.edu test_mem_mode = 'timing' 992957SN/Aelif options.detailed: 1003395Shsul@eecs.umich.edu CPUClass = DerivO3CPU 1013395Shsul@eecs.umich.edu test_mem_mode = 'timing' 1022957SN/Aelse: 1033395Shsul@eecs.umich.edu CPUClass = AtomicSimpleCPU 1043395Shsul@eecs.umich.edu test_mem_mode = 'atomic' 1052957SN/A 1063395Shsul@eecs.umich.eduCPUClass.clock = '2GHz' 1073005Sstever@eecs.umich.edu 1083395Shsul@eecs.umich.edunp = options.num_cpus 1093395Shsul@eecs.umich.edu 1103395Shsul@eecs.umich.edusystem = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], 1113323Shsul@eecs.umich.edu physmem = PhysicalMemory(range=AddrRange("512MB")), 1123395Shsul@eecs.umich.edu membus = Bus(), mem_mode = test_mem_mode) 1133395Shsul@eecs.umich.edu 1143005Sstever@eecs.umich.edusystem.physmem.port = system.membus.port 1153395Shsul@eecs.umich.edu 1163395Shsul@eecs.umich.edufor i in xrange(np): 1173395Shsul@eecs.umich.edu if options.caches and not options.standard_switch: 1183395Shsul@eecs.umich.edu system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), 1193448Shsul@eecs.umich.edu L1Cache(size = '64kB')) 1203395Shsul@eecs.umich.edu system.cpu[i].connectMemPorts(system.membus) 1213395Shsul@eecs.umich.edu system.cpu[i].mem = system.physmem 1223395Shsul@eecs.umich.edu system.cpu[i].workload = process 1233005Sstever@eecs.umich.edu 1243005Sstever@eecs.umich.eduroot = Root(system = system) 1252902SN/A 1263395Shsul@eecs.umich.eduSimulation.run(options, root, system) 127