ruby_random_test.py revision 8932
17635SBrad.Beckmann@amd.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 27635SBrad.Beckmann@amd.com# Copyright (c) 2009 Advanced Micro Devices, Inc. 37635SBrad.Beckmann@amd.com# All rights reserved. 47635SBrad.Beckmann@amd.com# 57635SBrad.Beckmann@amd.com# Redistribution and use in source and binary forms, with or without 67635SBrad.Beckmann@amd.com# modification, are permitted provided that the following conditions are 77635SBrad.Beckmann@amd.com# met: redistributions of source code must retain the above copyright 87635SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer; 97635SBrad.Beckmann@amd.com# redistributions in binary form must reproduce the above copyright 107635SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer in the 117635SBrad.Beckmann@amd.com# documentation and/or other materials provided with the distribution; 127635SBrad.Beckmann@amd.com# neither the name of the copyright holders nor the names of its 137635SBrad.Beckmann@amd.com# contributors may be used to endorse or promote products derived from 147635SBrad.Beckmann@amd.com# this software without specific prior written permission. 157635SBrad.Beckmann@amd.com# 167635SBrad.Beckmann@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 177635SBrad.Beckmann@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 187635SBrad.Beckmann@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 197635SBrad.Beckmann@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 207635SBrad.Beckmann@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 217635SBrad.Beckmann@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 227635SBrad.Beckmann@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 237635SBrad.Beckmann@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 247635SBrad.Beckmann@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 257635SBrad.Beckmann@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 267635SBrad.Beckmann@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 277635SBrad.Beckmann@amd.com# 287635SBrad.Beckmann@amd.com# Authors: Ron Dreslinski 297635SBrad.Beckmann@amd.com# Brad Beckmann 307635SBrad.Beckmann@amd.com 317635SBrad.Beckmann@amd.comimport m5 327635SBrad.Beckmann@amd.comfrom m5.objects import * 337635SBrad.Beckmann@amd.comfrom m5.defines import buildEnv 347635SBrad.Beckmann@amd.comfrom m5.util import addToPath 357635SBrad.Beckmann@amd.comimport os, optparse, sys 367635SBrad.Beckmann@amd.comaddToPath('../common') 377635SBrad.Beckmann@amd.comaddToPath('../ruby') 387635SBrad.Beckmann@amd.com 398928Sandreas.hansson@arm.comimport Options 407635SBrad.Beckmann@amd.comimport Ruby 417635SBrad.Beckmann@amd.com 427635SBrad.Beckmann@amd.com# Get paths we might need. It's expected this file is in m5/configs/example. 437635SBrad.Beckmann@amd.comconfig_path = os.path.dirname(os.path.abspath(__file__)) 447635SBrad.Beckmann@amd.comconfig_root = os.path.dirname(config_path) 457635SBrad.Beckmann@amd.comm5_root = os.path.dirname(config_root) 467635SBrad.Beckmann@amd.com 477635SBrad.Beckmann@amd.comparser = optparse.OptionParser() 488928Sandreas.hansson@arm.comOptions.addCommonOptions(parser) 497635SBrad.Beckmann@amd.com 507635SBrad.Beckmann@amd.comparser.add_option("-l", "--checks", metavar="N", default=100, 517635SBrad.Beckmann@amd.com help="Stop after N checks (loads)") 527635SBrad.Beckmann@amd.comparser.add_option("-f", "--wakeup_freq", metavar="N", default=10, 537635SBrad.Beckmann@amd.com help="Wakeup every N cycles") 547635SBrad.Beckmann@amd.com 557635SBrad.Beckmann@amd.com# 567635SBrad.Beckmann@amd.com# Add the ruby specific and protocol specific options 577635SBrad.Beckmann@amd.com# 587635SBrad.Beckmann@amd.comRuby.define_options(parser) 597635SBrad.Beckmann@amd.com 607635SBrad.Beckmann@amd.comexecfile(os.path.join(config_root, "common", "Options.py")) 617635SBrad.Beckmann@amd.com 627635SBrad.Beckmann@amd.com(options, args) = parser.parse_args() 637635SBrad.Beckmann@amd.com 647635SBrad.Beckmann@amd.com# 657635SBrad.Beckmann@amd.com# Set the default cache size and associativity to be very small to encourage 667635SBrad.Beckmann@amd.com# races between requests and writebacks. 677635SBrad.Beckmann@amd.com# 687635SBrad.Beckmann@amd.comoptions.l1d_size="256B" 697635SBrad.Beckmann@amd.comoptions.l1i_size="256B" 707635SBrad.Beckmann@amd.comoptions.l2_size="512B" 717635SBrad.Beckmann@amd.comoptions.l3_size="1kB" 727635SBrad.Beckmann@amd.comoptions.l1d_assoc=2 737635SBrad.Beckmann@amd.comoptions.l1i_assoc=2 747635SBrad.Beckmann@amd.comoptions.l2_assoc=2 757635SBrad.Beckmann@amd.comoptions.l3_assoc=2 767635SBrad.Beckmann@amd.com 777635SBrad.Beckmann@amd.comif args: 787635SBrad.Beckmann@amd.com print "Error: script doesn't take any positional arguments" 797635SBrad.Beckmann@amd.com sys.exit(1) 807635SBrad.Beckmann@amd.com 817635SBrad.Beckmann@amd.com# 827635SBrad.Beckmann@amd.com# Create the ruby random tester 837635SBrad.Beckmann@amd.com# 848184Ssomayeh@cs.wisc.edu 858184Ssomayeh@cs.wisc.edu# Check the protocol 868184Ssomayeh@cs.wisc.educheck_flush = False 878184Ssomayeh@cs.wisc.eduif buildEnv['PROTOCOL'] == 'MOESI_hammer': 888184Ssomayeh@cs.wisc.edu check_flush = True 898184Ssomayeh@cs.wisc.edu 908184Ssomayeh@cs.wisc.edutester = RubyTester(check_flush = check_flush, 918184Ssomayeh@cs.wisc.edu checks_to_complete = options.checks, 928932SBrad.Beckmann@amd.com wakeup_frequency = options.wakeup_freq, 938932SBrad.Beckmann@amd.com num_cpus = options.num_cpus) 947635SBrad.Beckmann@amd.com 957635SBrad.Beckmann@amd.com# 968931Sandreas.hansson@arm.com# Create the M5 system. Note that the Memory Object isn't 977635SBrad.Beckmann@amd.com# actually used by the rubytester, but is included to support the 987635SBrad.Beckmann@amd.com# M5 memory size == Ruby memory size checks 997635SBrad.Beckmann@amd.com# 1008931Sandreas.hansson@arm.comsystem = System(tester = tester, physmem = SimpleMemory()) 1017635SBrad.Beckmann@amd.com 1028436SBrad.Beckmann@amd.comRuby.create_system(options, system) 1037635SBrad.Beckmann@amd.com 1048322Ssteve.reinhardt@amd.comassert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) 1057635SBrad.Beckmann@amd.com 1067635SBrad.Beckmann@amd.com# 1077635SBrad.Beckmann@amd.com# The tester is most effective when randomization is turned on and 1087635SBrad.Beckmann@amd.com# artifical delay is randomly inserted on messages 1097635SBrad.Beckmann@amd.com# 1107635SBrad.Beckmann@amd.comsystem.ruby.randomization = True 1117635SBrad.Beckmann@amd.com 1128322Ssteve.reinhardt@amd.comfor ruby_port in system.ruby._cpu_ruby_ports: 1137635SBrad.Beckmann@amd.com # 1148932SBrad.Beckmann@amd.com # Tie the ruby tester ports to the ruby cpu read and write ports 1157635SBrad.Beckmann@amd.com # 1168932SBrad.Beckmann@amd.com if ruby_port.support_data_reqs: 1178932SBrad.Beckmann@amd.com tester.cpuDataPort = ruby_port.slave 1188932SBrad.Beckmann@amd.com if ruby_port.support_inst_reqs: 1198932SBrad.Beckmann@amd.com tester.cpuInstPort = ruby_port.slave 1207635SBrad.Beckmann@amd.com 1217635SBrad.Beckmann@amd.com # 1227635SBrad.Beckmann@amd.com # Tell each sequencer this is the ruby tester so that it 1237635SBrad.Beckmann@amd.com # copies the subblock back to the checker 1247635SBrad.Beckmann@amd.com # 1257635SBrad.Beckmann@amd.com ruby_port.using_ruby_tester = True 1267635SBrad.Beckmann@amd.com 1278436SBrad.Beckmann@amd.com # 1288436SBrad.Beckmann@amd.com # Ruby doesn't need the backing image of memory when running with 1298436SBrad.Beckmann@amd.com # the tester. 1308436SBrad.Beckmann@amd.com # 1318436SBrad.Beckmann@amd.com ruby_port.access_phys_mem = False 1328436SBrad.Beckmann@amd.com 1337635SBrad.Beckmann@amd.com# ----------------------- 1347635SBrad.Beckmann@amd.com# run simulation 1357635SBrad.Beckmann@amd.com# ----------------------- 1367635SBrad.Beckmann@amd.com 1378801Sgblack@eecs.umich.eduroot = Root( full_system = False, system = system ) 1387635SBrad.Beckmann@amd.comroot.system.mem_mode = 'timing' 1397635SBrad.Beckmann@amd.com 1407635SBrad.Beckmann@amd.com# Not much point in this being higher than the L1 latency 1417635SBrad.Beckmann@amd.comm5.ticks.setGlobalFrequency('1ns') 1427635SBrad.Beckmann@amd.com 1437635SBrad.Beckmann@amd.com# instantiate configuration 1447635SBrad.Beckmann@amd.comm5.instantiate() 1457635SBrad.Beckmann@amd.com 1467635SBrad.Beckmann@amd.com# simulate until program terminates 1477635SBrad.Beckmann@amd.comexit_event = m5.simulate(options.maxtick) 1487635SBrad.Beckmann@amd.com 1497635SBrad.Beckmann@amd.comprint 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause() 150