ruby_random_test.py revision 8932
1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; 9# redistributions in binary form must reproduce the above copyright 10# notice, this list of conditions and the following disclaimer in the 11# documentation and/or other materials provided with the distribution; 12# neither the name of the copyright holders nor the names of its 13# contributors may be used to endorse or promote products derived from 14# this software without specific prior written permission. 15# 16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27# 28# Authors: Ron Dreslinski 29# Brad Beckmann 30 31import m5 32from m5.objects import * 33from m5.defines import buildEnv 34from m5.util import addToPath 35import os, optparse, sys 36addToPath('../common') 37addToPath('../ruby') 38 39import Options 40import Ruby 41 42# Get paths we might need. It's expected this file is in m5/configs/example. 43config_path = os.path.dirname(os.path.abspath(__file__)) 44config_root = os.path.dirname(config_path) 45m5_root = os.path.dirname(config_root) 46 47parser = optparse.OptionParser() 48Options.addCommonOptions(parser) 49 50parser.add_option("-l", "--checks", metavar="N", default=100, 51 help="Stop after N checks (loads)") 52parser.add_option("-f", "--wakeup_freq", metavar="N", default=10, 53 help="Wakeup every N cycles") 54 55# 56# Add the ruby specific and protocol specific options 57# 58Ruby.define_options(parser) 59 60execfile(os.path.join(config_root, "common", "Options.py")) 61 62(options, args) = parser.parse_args() 63 64# 65# Set the default cache size and associativity to be very small to encourage 66# races between requests and writebacks. 67# 68options.l1d_size="256B" 69options.l1i_size="256B" 70options.l2_size="512B" 71options.l3_size="1kB" 72options.l1d_assoc=2 73options.l1i_assoc=2 74options.l2_assoc=2 75options.l3_assoc=2 76 77if args: 78 print "Error: script doesn't take any positional arguments" 79 sys.exit(1) 80 81# 82# Create the ruby random tester 83# 84 85# Check the protocol 86check_flush = False 87if buildEnv['PROTOCOL'] == 'MOESI_hammer': 88 check_flush = True 89 90tester = RubyTester(check_flush = check_flush, 91 checks_to_complete = options.checks, 92 wakeup_frequency = options.wakeup_freq, 93 num_cpus = options.num_cpus) 94 95# 96# Create the M5 system. Note that the Memory Object isn't 97# actually used by the rubytester, but is included to support the 98# M5 memory size == Ruby memory size checks 99# 100system = System(tester = tester, physmem = SimpleMemory()) 101 102Ruby.create_system(options, system) 103 104assert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) 105 106# 107# The tester is most effective when randomization is turned on and 108# artifical delay is randomly inserted on messages 109# 110system.ruby.randomization = True 111 112for ruby_port in system.ruby._cpu_ruby_ports: 113 # 114 # Tie the ruby tester ports to the ruby cpu read and write ports 115 # 116 if ruby_port.support_data_reqs: 117 tester.cpuDataPort = ruby_port.slave 118 if ruby_port.support_inst_reqs: 119 tester.cpuInstPort = ruby_port.slave 120 121 # 122 # Tell each sequencer this is the ruby tester so that it 123 # copies the subblock back to the checker 124 # 125 ruby_port.using_ruby_tester = True 126 127 # 128 # Ruby doesn't need the backing image of memory when running with 129 # the tester. 130 # 131 ruby_port.access_phys_mem = False 132 133# ----------------------- 134# run simulation 135# ----------------------- 136 137root = Root( full_system = False, system = system ) 138root.system.mem_mode = 'timing' 139 140# Not much point in this being higher than the L1 latency 141m5.ticks.setGlobalFrequency('1ns') 142 143# instantiate configuration 144m5.instantiate() 145 146# simulate until program terminates 147exit_event = m5.simulate(options.maxtick) 148 149print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause() 150