ruby_direct_test.py revision 12564
16899SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 26899SN/A# Copyright (c) 2009 Advanced Micro Devices, Inc. 36899SN/A# All rights reserved. 46899SN/A# 56899SN/A# Redistribution and use in source and binary forms, with or without 66899SN/A# modification, are permitted provided that the following conditions are 76899SN/A# met: redistributions of source code must retain the above copyright 86899SN/A# notice, this list of conditions and the following disclaimer; 96899SN/A# redistributions in binary form must reproduce the above copyright 106899SN/A# notice, this list of conditions and the following disclaimer in the 116899SN/A# documentation and/or other materials provided with the distribution; 126899SN/A# neither the name of the copyright holders nor the names of its 136899SN/A# contributors may be used to endorse or promote products derived from 146899SN/A# this software without specific prior written permission. 156899SN/A# 166899SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176899SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186899SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196899SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206899SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216899SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226899SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236899SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246899SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256899SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266899SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276899SN/A# 286899SN/A# Authors: Ron Dreslinski 296899SN/A# Brad Beckmann 306899SN/A 3112564Sgabeblack@google.comfrom __future__ import print_function 3212564Sgabeblack@google.com 336899SN/Aimport m5 346899SN/Afrom m5.objects import * 356899SN/Afrom m5.defines import buildEnv 366899SN/Afrom m5.util import addToPath 376899SN/Aimport os, optparse, sys 3811682Sandreas.hansson@arm.com 3911670Sandreas.hansson@arm.comaddToPath('../') 406899SN/A 4111682Sandreas.hansson@arm.comfrom common import Options 4211670Sandreas.hansson@arm.comfrom ruby import Ruby 436899SN/A 446899SN/A# Get paths we might need. It's expected this file is in m5/configs/example. 456899SN/Aconfig_path = os.path.dirname(os.path.abspath(__file__)) 466899SN/Aconfig_root = os.path.dirname(config_path) 476899SN/Am5_root = os.path.dirname(config_root) 486899SN/A 496899SN/Aparser = optparse.OptionParser() 5011688Sandreas.hansson@arm.comOptions.addNoISAOptions(parser) 516899SN/A 5210524Snilay@cs.wisc.eduparser.add_option("--requests", metavar="N", default=100, 537553SN/A help="Stop after N requests") 546899SN/Aparser.add_option("-f", "--wakeup_freq", metavar="N", default=10, 556899SN/A help="Wakeup every N cycles") 569365Snilay@cs.wisc.eduparser.add_option("--test-type", type="choice", default="SeriesGetx", 579365Snilay@cs.wisc.edu choices = ["SeriesGetx", "SeriesGets", "SeriesGetMixed", 589365Snilay@cs.wisc.edu "Invalidate"], 599365Snilay@cs.wisc.edu help = "Type of test") 609365Snilay@cs.wisc.eduparser.add_option("--percent-writes", type="int", default=100, 619365Snilay@cs.wisc.edu help="percentage of accesses that should be writes") 626899SN/A 636899SN/A# 647538SN/A# Add the ruby specific and protocol specific options 656899SN/A# 667538SN/ARuby.define_options(parser) 676899SN/A(options, args) = parser.parse_args() 686899SN/A 696899SN/Aif args: 7012564Sgabeblack@google.com print("Error: script doesn't take any positional arguments") 716899SN/A sys.exit(1) 726899SN/A 736899SN/A# 747632SBrad.Beckmann@amd.com# Select the direct test generator 756899SN/A# 767553SN/Aif options.test_type == "SeriesGetx": 777553SN/A generator = SeriesRequestGenerator(num_cpus = options.num_cpus, 789365Snilay@cs.wisc.edu percent_writes = 100) 797553SN/Aelif options.test_type == "SeriesGets": 807553SN/A generator = SeriesRequestGenerator(num_cpus = options.num_cpus, 819365Snilay@cs.wisc.edu percent_writes = 0) 829365Snilay@cs.wisc.eduelif options.test_type == "SeriesGetMixed": 839365Snilay@cs.wisc.edu generator = SeriesRequestGenerator(num_cpus = options.num_cpus, 849365Snilay@cs.wisc.edu percent_writes = options.percent_writes) 857553SN/Aelif options.test_type == "Invalidate": 867553SN/A generator = InvalidateGenerator(num_cpus = options.num_cpus) 877553SN/Aelse: 8812564Sgabeblack@google.com print("Error: unknown direct test generator") 897553SN/A sys.exit(1) 906899SN/A 9110524Snilay@cs.wisc.edu# Create the M5 system. 9210524Snilay@cs.wisc.edusystem = System(mem_ranges = [AddrRange(options.mem_size)]) 939870Sandreas.hansson@arm.com 949870Sandreas.hansson@arm.com 959870Sandreas.hansson@arm.com# Create a top-level voltage domain and clock domain 969870Sandreas.hansson@arm.comsystem.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 979870Sandreas.hansson@arm.com 989870Sandreas.hansson@arm.comsystem.clk_domain = SrcClockDomain(clock = options.sys_clock, 999870Sandreas.hansson@arm.com voltage_domain = system.voltage_domain) 1009793Sakash.bagdia@arm.com 1017553SN/A# Create the ruby random tester 10210524Snilay@cs.wisc.edusystem.cpu = RubyDirectedTester(requests_to_complete = options.requests, 10310524Snilay@cs.wisc.edu generator = generator) 1047553SN/A 10510519Snilay@cs.wisc.eduRuby.create_system(options, False, system) 1066899SN/A 1079793Sakash.bagdia@arm.com# Since Ruby runs at an independent frequency, create a seperate clock 1089870Sandreas.hansson@arm.comsystem.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 1099870Sandreas.hansson@arm.com voltage_domain = system.voltage_domain) 1109793Sakash.bagdia@arm.com 11110120Snilay@cs.wisc.eduassert(options.num_cpus == len(system.ruby._cpu_ports)) 1126899SN/A 11310120Snilay@cs.wisc.edufor ruby_port in system.ruby._cpu_ports: 1146899SN/A # 1156899SN/A # Tie the ruby tester ports to the ruby cpu ports 1166899SN/A # 11710524Snilay@cs.wisc.edu system.cpu.cpuPort = ruby_port.slave 1186899SN/A 1196899SN/A# ----------------------- 1206899SN/A# run simulation 1216899SN/A# ----------------------- 1226899SN/A 1238801Sgblack@eecs.umich.eduroot = Root( full_system = False, system = system ) 1246899SN/Aroot.system.mem_mode = 'timing' 1256899SN/A 1266899SN/A# Not much point in this being higher than the L1 latency 1276899SN/Am5.ticks.setGlobalFrequency('1ns') 1286899SN/A 1296899SN/A# instantiate configuration 1307525SN/Am5.instantiate() 1316899SN/A 1326899SN/A# simulate until program terminates 1339909Snilay@cs.wisc.eduexit_event = m5.simulate(options.abs_max_tick) 1346899SN/A 13512564Sgabeblack@google.comprint('Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()) 136