ruby_direct_test.py revision 12564
1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; 9# redistributions in binary form must reproduce the above copyright 10# notice, this list of conditions and the following disclaimer in the 11# documentation and/or other materials provided with the distribution; 12# neither the name of the copyright holders nor the names of its 13# contributors may be used to endorse or promote products derived from 14# this software without specific prior written permission. 15# 16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27# 28# Authors: Ron Dreslinski 29# Brad Beckmann 30 31from __future__ import print_function 32 33import m5 34from m5.objects import * 35from m5.defines import buildEnv 36from m5.util import addToPath 37import os, optparse, sys 38 39addToPath('../') 40 41from common import Options 42from ruby import Ruby 43 44# Get paths we might need. It's expected this file is in m5/configs/example. 45config_path = os.path.dirname(os.path.abspath(__file__)) 46config_root = os.path.dirname(config_path) 47m5_root = os.path.dirname(config_root) 48 49parser = optparse.OptionParser() 50Options.addNoISAOptions(parser) 51 52parser.add_option("--requests", metavar="N", default=100, 53 help="Stop after N requests") 54parser.add_option("-f", "--wakeup_freq", metavar="N", default=10, 55 help="Wakeup every N cycles") 56parser.add_option("--test-type", type="choice", default="SeriesGetx", 57 choices = ["SeriesGetx", "SeriesGets", "SeriesGetMixed", 58 "Invalidate"], 59 help = "Type of test") 60parser.add_option("--percent-writes", type="int", default=100, 61 help="percentage of accesses that should be writes") 62 63# 64# Add the ruby specific and protocol specific options 65# 66Ruby.define_options(parser) 67(options, args) = parser.parse_args() 68 69if args: 70 print("Error: script doesn't take any positional arguments") 71 sys.exit(1) 72 73# 74# Select the direct test generator 75# 76if options.test_type == "SeriesGetx": 77 generator = SeriesRequestGenerator(num_cpus = options.num_cpus, 78 percent_writes = 100) 79elif options.test_type == "SeriesGets": 80 generator = SeriesRequestGenerator(num_cpus = options.num_cpus, 81 percent_writes = 0) 82elif options.test_type == "SeriesGetMixed": 83 generator = SeriesRequestGenerator(num_cpus = options.num_cpus, 84 percent_writes = options.percent_writes) 85elif options.test_type == "Invalidate": 86 generator = InvalidateGenerator(num_cpus = options.num_cpus) 87else: 88 print("Error: unknown direct test generator") 89 sys.exit(1) 90 91# Create the M5 system. 92system = System(mem_ranges = [AddrRange(options.mem_size)]) 93 94 95# Create a top-level voltage domain and clock domain 96system.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 97 98system.clk_domain = SrcClockDomain(clock = options.sys_clock, 99 voltage_domain = system.voltage_domain) 100 101# Create the ruby random tester 102system.cpu = RubyDirectedTester(requests_to_complete = options.requests, 103 generator = generator) 104 105Ruby.create_system(options, False, system) 106 107# Since Ruby runs at an independent frequency, create a seperate clock 108system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 109 voltage_domain = system.voltage_domain) 110 111assert(options.num_cpus == len(system.ruby._cpu_ports)) 112 113for ruby_port in system.ruby._cpu_ports: 114 # 115 # Tie the ruby tester ports to the ruby cpu ports 116 # 117 system.cpu.cpuPort = ruby_port.slave 118 119# ----------------------- 120# run simulation 121# ----------------------- 122 123root = Root( full_system = False, system = system ) 124root.system.mem_mode = 'timing' 125 126# Not much point in this being higher than the L1 latency 127m5.ticks.setGlobalFrequency('1ns') 128 129# instantiate configuration 130m5.instantiate() 131 132# simulate until program terminates 133exit_event = m5.simulate(options.abs_max_tick) 134 135print('Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()) 136