memtest.py revision 4892:298bc09b72fa 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Ron Dreslinski
28
29import m5
30from m5.objects import *
31import os, optparse, sys
32m5.AddToPath('../common')
33
34parser = optparse.OptionParser()
35
36parser.add_option("-a", "--atomic", action="store_true",
37                  help="Use atomic (non-timing) mode")
38parser.add_option("-b", "--blocking", action="store_true",
39                  help="Use blocking caches")
40parser.add_option("-l", "--maxloads", metavar="N",
41                  help="Stop after N loads")
42parser.add_option("-m", "--maxtick", type="int", default=m5.MaxTick,
43                  metavar="T",
44                  help="Stop after T ticks")
45
46#
47# The "tree" specification is a colon-separated list of one or more
48# integers.  The first integer is the number of caches/testers
49# connected directly to main memory.  The last integer in the list is
50# the number of testers associated with the uppermost level of memory
51# (L1 cache, if there are caches, or main memory if no caches).  Thus
52# if there is only one integer, there are no caches, and the integer
53# specifies the number of testers connected directly to main memory.
54# The other integers (if any) specify the number of caches at each
55# level of the hierarchy between.
56#
57# Examples:
58#
59#  "2:1"    Two caches connected to memory with a single tester behind each
60#           (single-level hierarchy, two testers total)
61#
62#  "2:2:1"  Two-level hierarchy, 2 L1s behind each of 2 L2s, 4 testers total
63#
64parser.add_option("-t", "--treespec", type="string", default="8:1",
65                  help="Colon-separated multilevel tree specification, "
66                  "see script comments for details "
67                  "[default: %default]")
68
69parser.add_option("--force-bus", action="store_true",
70                  help="Use bus between levels even with single cache")
71
72parser.add_option("-f", "--functional", type="int", default=0,
73                  metavar="PCT",
74                  help="Target percentage of functional accesses "
75                  "[default: %default]")
76parser.add_option("-u", "--uncacheable", type="int", default=0,
77                  metavar="PCT",
78                  help="Target percentage of uncacheable accesses "
79                  "[default: %default]")
80
81parser.add_option("--progress", type="int", default=1000,
82                  metavar="NLOADS",
83                  help="Progress message interval "
84                  "[default: %default]")
85
86(options, args) = parser.parse_args()
87
88if args:
89     print "Error: script doesn't take any positional arguments"
90     sys.exit(1)
91
92block_size = 64
93
94try:
95     treespec = [int(x) for x in options.treespec.split(':')]
96     numtesters = reduce(lambda x,y: x*y, treespec)
97except:
98     print "Error parsing treespec option"
99     sys.exit(1)
100
101if numtesters > block_size:
102     print "Error: Number of testers limited to %s because of false sharing" \
103           % (block_size)
104     sys.exit(1)
105
106if len(treespec) < 1:
107     print "Error parsing treespec"
108     sys.exit(1)
109
110# define prototype L1 cache
111proto_l1 = BaseCache(size = '32kB', assoc = 4, block_size = block_size,
112                     latency = '1ns', tgts_per_mshr = 8)
113
114if options.blocking:
115     proto_l1.mshrs = 1
116else:
117     proto_l1.mshrs = 8
118
119# build a list of prototypes, one for each cache level (L1 is at end,
120# followed by the tester pseudo-cpu objects)
121prototypes = [ proto_l1,
122               MemTest(atomic=options.atomic, max_loads=options.maxloads,
123                       percent_functional=options.functional,
124                       percent_uncacheable=options.uncacheable,
125                       progress_interval=options.progress) ]
126
127while len(prototypes) < len(treespec):
128     # clone previous level and update params
129     prev = prototypes[0]
130     next = prev()
131     next.size = prev.size * 4
132     next.latency = prev.latency * 10
133     next.assoc = prev.assoc * 2
134     prototypes.insert(0, next)
135
136# system simulated
137system = System(funcmem = PhysicalMemory(),
138                physmem = PhysicalMemory(latency = "100ns"))
139
140def make_level(spec, prototypes, attach_obj, attach_port):
141     fanout = spec[0]
142     parent = attach_obj # use attach obj as config parent too
143     if fanout > 1 or options.force_bus:
144          new_bus = Bus(clock="500MHz", width=16)
145          new_bus.port = getattr(attach_obj, attach_port)
146          parent.cpu_side_bus = new_bus
147          attach_obj = new_bus
148          attach_port = "port"
149     objs = [prototypes[0]() for i in xrange(fanout)]
150     if len(spec) > 1:
151          # we just built caches, more levels to go
152          parent.cache = objs
153          for cache in objs:
154               cache.mem_side = getattr(attach_obj, attach_port)
155               make_level(spec[1:], prototypes[1:], cache, "cpu_side")
156     else:
157          # we just built the MemTest objects
158          parent.cpu = objs
159          for t in objs:
160               t.test = getattr(attach_obj, attach_port)
161               t.functional = system.funcmem.port
162
163make_level(treespec, prototypes, system.physmem, "port")
164
165# -----------------------
166# run simulation
167# -----------------------
168
169root = Root( system = system )
170if options.atomic:
171    root.system.mem_mode = 'atomic'
172else:
173    root.system.mem_mode = 'timing'
174
175# Not much point in this being higher than the L1 latency
176m5.ticks.setGlobalFrequency('1ns')
177
178# instantiate configuration
179m5.instantiate(root)
180
181# simulate until program terminates
182exit_event = m5.simulate(options.maxtick)
183
184print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
185