memtest.py revision 11722:f15f02d8c79e
16145Snate@binkert.org# Copyright (c) 2015 ARM Limited 26145Snate@binkert.org# All rights reserved. 36145Snate@binkert.org# 46145Snate@binkert.org# The license below extends only to copyright in the software and shall 56145Snate@binkert.org# not be construed as granting a license to any other intellectual 66145Snate@binkert.org# property including but not limited to intellectual property relating 76145Snate@binkert.org# to a hardware implementation of the functionality of the software 86145Snate@binkert.org# licensed hereunder. You may use the software subject to the license 96145Snate@binkert.org# terms below provided that you ensure that this notice is replicated 106145Snate@binkert.org# unmodified and in its entirety in all distributions of the software, 116145Snate@binkert.org# modified or unmodified, in source code or in binary form. 126145Snate@binkert.org# 136145Snate@binkert.org# Copyright (c) 2006-2007 The Regents of The University of Michigan 146145Snate@binkert.org# All rights reserved. 156145Snate@binkert.org# 166145Snate@binkert.org# Redistribution and use in source and binary forms, with or without 176145Snate@binkert.org# modification, are permitted provided that the following conditions are 186145Snate@binkert.org# met: redistributions of source code must retain the above copyright 196145Snate@binkert.org# notice, this list of conditions and the following disclaimer; 206145Snate@binkert.org# redistributions in binary form must reproduce the above copyright 216145Snate@binkert.org# notice, this list of conditions and the following disclaimer in the 226145Snate@binkert.org# documentation and/or other materials provided with the distribution; 236145Snate@binkert.org# neither the name of the copyright holders nor the names of its 246145Snate@binkert.org# contributors may be used to endorse or promote products derived from 256145Snate@binkert.org# this software without specific prior written permission. 266145Snate@binkert.org# 276145Snate@binkert.org# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 286145Snate@binkert.org# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 296145Snate@binkert.org# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 306145Snate@binkert.org# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 316145Snate@binkert.org# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 326145Snate@binkert.org# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 336145Snate@binkert.org# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 346145Snate@binkert.org# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 356145Snate@binkert.org# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 366145Snate@binkert.org# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 376145Snate@binkert.org# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 386145Snate@binkert.org# 396145Snate@binkert.org# Authors: Ron Dreslinski 406145Snate@binkert.org# Andreas Hansson 416145Snate@binkert.org 426145Snate@binkert.orgimport optparse 436145Snate@binkert.orgimport random 446145Snate@binkert.orgimport sys 456145Snate@binkert.org 466145Snate@binkert.orgimport m5 476145Snate@binkert.orgfrom m5.objects import * 486145Snate@binkert.org 496145Snate@binkert.org# This example script stress tests the memory system by creating false 506145Snate@binkert.org# sharing in a tree topology. At the bottom of the tree is a shared 516145Snate@binkert.org# memory, and then at each level a number of testers are attached, 526145Snate@binkert.org# along with a number of caches that them selves fan out to subtrees 536145Snate@binkert.org# of testers and caches. Thus, it is possible to create a system with 546145Snate@binkert.org# arbitrarily deep cache hierarchies, sharing or no sharing of caches, 556145Snate@binkert.org# and testers not only at the L1s, but also at the L2s, L3s etc. 566145Snate@binkert.org 576145Snate@binkert.orgparser = optparse.OptionParser() 586145Snate@binkert.org 596145Snate@binkert.orgparser.add_option("-a", "--atomic", action="store_true", 606145Snate@binkert.org help="Use atomic (non-timing) mode") 616145Snate@binkert.orgparser.add_option("-b", "--blocking", action="store_true", 626145Snate@binkert.org help="Use blocking caches") 636145Snate@binkert.orgparser.add_option("-l", "--maxloads", metavar="N", default=0, 646145Snate@binkert.org help="Stop after N loads") 656145Snate@binkert.orgparser.add_option("-m", "--maxtick", type="int", default=m5.MaxTick, 666145Snate@binkert.org metavar="T", 676145Snate@binkert.org help="Stop after T ticks") 686145Snate@binkert.org 696145Snate@binkert.org# The tree specification consists of two colon-separated lists of one 706145Snate@binkert.org# or more integers, one for the caches, and one for the testers. The 716145Snate@binkert.org# first integer is the number of caches/testers closest to main 726145Snate@binkert.org# memory. Each cache then fans out to a subtree. The last integer in 736145Snate@binkert.org# the list is the number of caches/testers associated with the 746145Snate@binkert.org# uppermost level of memory. The other integers (if any) specify the 756145Snate@binkert.org# number of caches/testers connected at each level of the crossbar 766145Snate@binkert.org# hierarchy. The tester string should have one element more than the 776145Snate@binkert.org# cache string as there should always be testers attached to the 786145Snate@binkert.org# uppermost caches. 796145Snate@binkert.org 806145Snate@binkert.orgparser.add_option("-c", "--caches", type="string", default="2:2:1", 816145Snate@binkert.org help="Colon-separated cache hierarchy specification, " 826145Snate@binkert.org "see script comments for details " 836145Snate@binkert.org "[default: %default]") 846145Snate@binkert.orgparser.add_option("-t", "--testers", type="string", default="1:1:0:2", 856145Snate@binkert.org help="Colon-separated tester hierarchy specification, " 866145Snate@binkert.org "see script comments for details " 876145Snate@binkert.org "[default: %default]") 886145Snate@binkert.orgparser.add_option("-f", "--functional", type="int", default=10, 896145Snate@binkert.org metavar="PCT", 906145Snate@binkert.org help="Target percentage of functional accesses " 916145Snate@binkert.org "[default: %default]") 926145Snate@binkert.orgparser.add_option("-u", "--uncacheable", type="int", default=10, 936145Snate@binkert.org metavar="PCT", 946145Snate@binkert.org help="Target percentage of uncacheable accesses " 956145Snate@binkert.org "[default: %default]") 966145Snate@binkert.orgparser.add_option("-r", "--random", action="store_true", 976145Snate@binkert.org help="Generate a random tree topology") 986145Snate@binkert.orgparser.add_option("--progress", type="int", default=100000, 996145Snate@binkert.org metavar="NLOADS", 1006145Snate@binkert.org help="Progress message interval " 1016145Snate@binkert.org "[default: %default]") 1026145Snate@binkert.orgparser.add_option("--sys-clock", action="store", type="string", 1036145Snate@binkert.org default='1GHz', 1046145Snate@binkert.org help = """Top-level clock for blocks running at system 1056145Snate@binkert.org speed""") 1066145Snate@binkert.org 1076145Snate@binkert.org(options, args) = parser.parse_args() 1086145Snate@binkert.org 1096145Snate@binkert.orgif args: 1106145Snate@binkert.org print "Error: script doesn't take any positional arguments" 1116145Snate@binkert.org sys.exit(1) 1126145Snate@binkert.org 1136145Snate@binkert.org# Get the total number of testers 1146145Snate@binkert.orgdef numtesters(cachespec, testerspec): 1156145Snate@binkert.org # Determine the tester multiplier for each level as the 1166145Snate@binkert.org # elements are per subsystem and it fans out 1176145Snate@binkert.org multiplier = [1] 1186145Snate@binkert.org for c in cachespec: 1196145Snate@binkert.org multiplier.append(multiplier[-1] * c) 1206145Snate@binkert.org 1216145Snate@binkert.org total = 0 1226145Snate@binkert.org for t, m in zip(testerspec, multiplier): 1236145Snate@binkert.org total += t * m 1246145Snate@binkert.org 1256145Snate@binkert.org return total 1266145Snate@binkert.org 1276145Snate@binkert.orgblock_size = 64 1286145Snate@binkert.org 1296145Snate@binkert.org# Start by parsing the command line options and do some basic sanity 1306145Snate@binkert.org# checking 1316145Snate@binkert.orgif options.random: 1326145Snate@binkert.org # Generate a tree with a valid number of testers 1336145Snate@binkert.org while True: 1346145Snate@binkert.org tree_depth = random.randint(1, 4) 1356145Snate@binkert.org cachespec = [random.randint(1, 3) for i in range(tree_depth)] 1366145Snate@binkert.org testerspec = [random.randint(1, 3) for i in range(tree_depth + 1)] 1376145Snate@binkert.org if numtesters(cachespec, testerspec) < block_size: 1386145Snate@binkert.org break 1396145Snate@binkert.org 1406145Snate@binkert.org print "Generated random tree -c", ':'.join(map(str, cachespec)), \ 1416145Snate@binkert.org "-t", ':'.join(map(str, testerspec)) 1426145Snate@binkert.orgelse: 1436145Snate@binkert.org try: 1446145Snate@binkert.org cachespec = [int(x) for x in options.caches.split(':')] 1456145Snate@binkert.org testerspec = [int(x) for x in options.testers.split(':')] 146 except: 147 print "Error: Unable to parse caches or testers option" 148 sys.exit(1) 149 150 if len(cachespec) < 1: 151 print "Error: Must have at least one level of caches" 152 sys.exit(1) 153 154 if len(cachespec) != len(testerspec) - 1: 155 print "Error: Testers must have one element more than caches" 156 sys.exit(1) 157 158 if testerspec[-1] == 0: 159 print "Error: Must have testers at the uppermost level" 160 sys.exit(1) 161 162 for t in testerspec: 163 if t < 0: 164 print "Error: Cannot have a negative number of testers" 165 sys.exit(1) 166 167 for c in cachespec: 168 if c < 1: 169 print "Error: Must have 1 or more caches at each level" 170 sys.exit(1) 171 172 if numtesters(cachespec, testerspec) > block_size: 173 print "Error: Limited to %s testers because of false sharing" \ 174 % (block_size) 175 sys.exit(1) 176 177# Define a prototype L1 cache that we scale for all successive levels 178proto_l1 = Cache(size = '32kB', assoc = 4, 179 tag_latency = 1, data_latency = 1, response_latency = 1, 180 tgts_per_mshr = 8, clusivity = 'mostly_incl', 181 writeback_clean = True) 182 183if options.blocking: 184 proto_l1.mshrs = 1 185else: 186 proto_l1.mshrs = 4 187 188cache_proto = [proto_l1] 189 190# Now add additional cache levels (if any) by scaling L1 params, the 191# first element is Ln, and the last element L1 192for scale in cachespec[:-1]: 193 # Clone previous level and update params 194 prev = cache_proto[0] 195 next = prev() 196 next.size = prev.size * scale 197 next.tag_latency = prev.tag_latency * 10 198 next.data_latency = prev.data_latency * 10 199 next.response_latency = prev.response_latency * 10 200 next.assoc = prev.assoc * scale 201 next.mshrs = prev.mshrs * scale 202 203 # Swap the inclusivity/exclusivity at each level. L2 is mostly 204 # exclusive with respect to L1, L3 mostly inclusive, L4 mostly 205 # exclusive etc. 206 next.writeback_clean = not prev.writeback_clean 207 if (prev.clusivity.value == 'mostly_incl'): 208 next.clusivity = 'mostly_excl' 209 else: 210 next.clusivity = 'mostly_incl' 211 212 cache_proto.insert(0, next) 213 214# Make a prototype for the tester to be used throughout 215proto_tester = MemTest(max_loads = options.maxloads, 216 percent_functional = options.functional, 217 percent_uncacheable = options.uncacheable, 218 progress_interval = options.progress) 219 220# Set up the system along with a simple memory and reference memory 221system = System(physmem = SimpleMemory(), 222 cache_line_size = block_size) 223 224system.voltage_domain = VoltageDomain(voltage = '1V') 225 226system.clk_domain = SrcClockDomain(clock = options.sys_clock, 227 voltage_domain = system.voltage_domain) 228 229# For each level, track the next subsys index to use 230next_subsys_index = [0] * (len(cachespec) + 1) 231 232# Recursive function to create a sub-tree of the cache and tester 233# hierarchy 234def make_cache_level(ncaches, prototypes, level, next_cache): 235 global next_subsys_index, proto_l1, testerspec, proto_tester 236 237 index = next_subsys_index[level] 238 next_subsys_index[level] += 1 239 240 # Create a subsystem to contain the crossbar and caches, and 241 # any testers 242 subsys = SubSystem() 243 setattr(system, 'l%dsubsys%d' % (level, index), subsys) 244 245 # The levels are indexing backwards through the list 246 ntesters = testerspec[len(cachespec) - level] 247 248 # Scale the progress threshold as testers higher up in the tree 249 # (smaller level) get a smaller portion of the overall bandwidth, 250 # and also make the interval of packet injection longer for the 251 # testers closer to the memory (larger level) to prevent them 252 # hogging all the bandwidth 253 limit = (len(cachespec) - level + 1) * 100000000 254 testers = [proto_tester(interval = 10 * (level * level + 1), 255 progress_check = limit) \ 256 for i in xrange(ntesters)] 257 if ntesters: 258 subsys.tester = testers 259 260 if level != 0: 261 # Create a crossbar and add it to the subsystem, note that 262 # we do this even with a single element on this level 263 xbar = L2XBar() 264 subsys.xbar = xbar 265 if next_cache: 266 xbar.master = next_cache.cpu_side 267 268 # Create and connect the caches, both the ones fanning out 269 # to create the tree, and the ones used to connect testers 270 # on this level 271 tree_caches = [prototypes[0]() for i in xrange(ncaches[0])] 272 tester_caches = [proto_l1() for i in xrange(ntesters)] 273 274 subsys.cache = tester_caches + tree_caches 275 for cache in tree_caches: 276 cache.mem_side = xbar.slave 277 make_cache_level(ncaches[1:], prototypes[1:], level - 1, cache) 278 for tester, cache in zip(testers, tester_caches): 279 tester.port = cache.cpu_side 280 cache.mem_side = xbar.slave 281 else: 282 if not next_cache: 283 print "Error: No next-level cache at top level" 284 sys.exit(1) 285 286 if ntesters > 1: 287 # Create a crossbar and add it to the subsystem 288 xbar = L2XBar() 289 subsys.xbar = xbar 290 xbar.master = next_cache.cpu_side 291 for tester in testers: 292 tester.port = xbar.slave 293 else: 294 # Single tester 295 testers[0].port = next_cache.cpu_side 296 297# Top level call to create the cache hierarchy, bottom up 298make_cache_level(cachespec, cache_proto, len(cachespec), None) 299 300# Connect the lowest level crossbar to the memory 301last_subsys = getattr(system, 'l%dsubsys0' % len(cachespec)) 302last_subsys.xbar.master = system.physmem.port 303last_subsys.xbar.point_of_coherency = True 304 305root = Root(full_system = False, system = system) 306if options.atomic: 307 root.system.mem_mode = 'atomic' 308else: 309 root.system.mem_mode = 'timing' 310 311# The system port is never used in the tester so merely connect it 312# to avoid problems 313root.system.system_port = last_subsys.xbar.slave 314 315# Instantiate configuration 316m5.instantiate() 317 318# Simulate until program terminates 319exit_event = m5.simulate(options.maxtick) 320 321print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause() 322