memtest.py revision 11198:8149b36b8803
1# Copyright (c) 2015 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2006-2007 The Regents of The University of Michigan 14# All rights reserved. 15# 16# Redistribution and use in source and binary forms, with or without 17# modification, are permitted provided that the following conditions are 18# met: redistributions of source code must retain the above copyright 19# notice, this list of conditions and the following disclaimer; 20# redistributions in binary form must reproduce the above copyright 21# notice, this list of conditions and the following disclaimer in the 22# documentation and/or other materials provided with the distribution; 23# neither the name of the copyright holders nor the names of its 24# contributors may be used to endorse or promote products derived from 25# this software without specific prior written permission. 26# 27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Ron Dreslinski 40# Andreas Hansson 41 42import optparse 43import random 44import sys 45 46import m5 47from m5.objects import * 48 49# This example script stress tests the memory system by creating false 50# sharing in a tree topology. At the bottom of the tree is a shared 51# memory, and then at each level a number of testers are attached, 52# along with a number of caches that them selves fan out to subtrees 53# of testers and caches. Thus, it is possible to create a system with 54# arbitrarily deep cache hierarchies, sharing or no sharing of caches, 55# and testers not only at the L1s, but also at the L2s, L3s etc. 56 57parser = optparse.OptionParser() 58 59parser.add_option("-a", "--atomic", action="store_true", 60 help="Use atomic (non-timing) mode") 61parser.add_option("-b", "--blocking", action="store_true", 62 help="Use blocking caches") 63parser.add_option("-l", "--maxloads", metavar="N", default=0, 64 help="Stop after N loads") 65parser.add_option("-m", "--maxtick", type="int", default=m5.MaxTick, 66 metavar="T", 67 help="Stop after T ticks") 68 69# The tree specification consists of two colon-separated lists of one 70# or more integers, one for the caches, and one for the testers. The 71# first integer is the number of caches/testers closest to main 72# memory. Each cache then fans out to a subtree. The last integer in 73# the list is the number of caches/testers associated with the 74# uppermost level of memory. The other integers (if any) specify the 75# number of caches/testers connected at each level of the crossbar 76# hierarchy. The tester string should have one element more than the 77# cache string as there should always be testers attached to the 78# uppermost caches. 79 80parser.add_option("-c", "--caches", type="string", default="2:2:1", 81 help="Colon-separated cache hierarchy specification, " 82 "see script comments for details " 83 "[default: %default]") 84parser.add_option("-t", "--testers", type="string", default="1:1:0:2", 85 help="Colon-separated tester hierarchy specification, " 86 "see script comments for details " 87 "[default: %default]") 88parser.add_option("-f", "--functional", type="int", default=0, 89 metavar="PCT", 90 help="Target percentage of functional accesses " 91 "[default: %default]") 92parser.add_option("-u", "--uncacheable", type="int", default=0, 93 metavar="PCT", 94 help="Target percentage of uncacheable accesses " 95 "[default: %default]") 96parser.add_option("-r", "--random", action="store_true", 97 help="Generate a random tree topology") 98parser.add_option("--progress", type="int", default=100000, 99 metavar="NLOADS", 100 help="Progress message interval " 101 "[default: %default]") 102parser.add_option("--sys-clock", action="store", type="string", 103 default='1GHz', 104 help = """Top-level clock for blocks running at system 105 speed""") 106 107(options, args) = parser.parse_args() 108 109if args: 110 print "Error: script doesn't take any positional arguments" 111 sys.exit(1) 112 113# Get the total number of testers 114def numtesters(cachespec, testerspec): 115 # Determine the tester multiplier for each level as the 116 # elements are per subsystem and it fans out 117 multiplier = [1] 118 for c in cachespec: 119 multiplier.append(multiplier[-1] * c) 120 121 total = 0 122 for t, m in zip(testerspec, multiplier): 123 total += t * m 124 125 return total 126 127block_size = 64 128 129# Start by parsing the command line options and do some basic sanity 130# checking 131if options.random: 132 # Generate a tree with a valid number of testers 133 while True: 134 tree_depth = random.randint(1, 4) 135 cachespec = [random.randint(1, 3) for i in range(tree_depth)] 136 testerspec = [random.randint(1, 3) for i in range(tree_depth + 1)] 137 if numtesters(cachespec, testerspec) < block_size: 138 break 139 140 print "Generated random tree -c", ':'.join(map(str, cachespec)), \ 141 "-t", ':'.join(map(str, testerspec)) 142else: 143 try: 144 cachespec = [int(x) for x in options.caches.split(':')] 145 testerspec = [int(x) for x in options.testers.split(':')] 146 except: 147 print "Error: Unable to parse caches or testers option" 148 sys.exit(1) 149 150 if len(cachespec) < 1: 151 print "Error: Must have at least one level of caches" 152 sys.exit(1) 153 154 if len(cachespec) != len(testerspec) - 1: 155 print "Error: Testers must have one element more than caches" 156 sys.exit(1) 157 158 if testerspec[-1] == 0: 159 print "Error: Must have testers at the uppermost level" 160 sys.exit(1) 161 162 for t in testerspec: 163 if t < 0: 164 print "Error: Cannot have a negative number of testers" 165 sys.exit(1) 166 167 for c in cachespec: 168 if c < 1: 169 print "Error: Must have 1 or more caches at each level" 170 sys.exit(1) 171 172 if numtesters(cachespec, testerspec) > block_size: 173 print "Error: Limited to %s testers because of false sharing" \ 174 % (block_size) 175 sys.exit(1) 176 177# Define a prototype L1 cache that we scale for all successive levels 178proto_l1 = Cache(size = '32kB', assoc = 4, 179 hit_latency = 1, response_latency = 1, 180 tgts_per_mshr = 8, clusivity = 'mostly_incl') 181 182if options.blocking: 183 proto_l1.mshrs = 1 184else: 185 proto_l1.mshrs = 4 186 187cache_proto = [proto_l1] 188 189# Now add additional cache levels (if any) by scaling L1 params, the 190# first element is Ln, and the last element L1 191for scale in cachespec[:-1]: 192 # Clone previous level and update params 193 prev = cache_proto[0] 194 next = prev() 195 next.size = prev.size * scale 196 next.hit_latency = prev.hit_latency * 10 197 next.response_latency = prev.response_latency * 10 198 next.assoc = prev.assoc * scale 199 next.mshrs = prev.mshrs * scale 200 201 # Swap the inclusivity/exclusivity at each level. L2 is mostly 202 # exclusive with respect to L1, L3 mostly inclusive, L4 mostly 203 # exclusive etc. 204 if (prev.clusivity.value == 'mostly_incl'): 205 next.clusivity = 'mostly_excl' 206 else: 207 next.clusivity = 'mostly_incl' 208 209 cache_proto.insert(0, next) 210 211# Make a prototype for the tester to be used throughout 212proto_tester = MemTest(max_loads = options.maxloads, 213 percent_functional = options.functional, 214 percent_uncacheable = options.uncacheable, 215 progress_interval = options.progress) 216 217# Set up the system along with a simple memory and reference memory 218system = System(physmem = SimpleMemory(), 219 cache_line_size = block_size) 220 221system.voltage_domain = VoltageDomain(voltage = '1V') 222 223system.clk_domain = SrcClockDomain(clock = options.sys_clock, 224 voltage_domain = system.voltage_domain) 225 226# For each level, track the next subsys index to use 227next_subsys_index = [0] * (len(cachespec) + 1) 228 229# Recursive function to create a sub-tree of the cache and tester 230# hierarchy 231def make_cache_level(ncaches, prototypes, level, next_cache): 232 global next_subsys_index, proto_l1, testerspec, proto_tester 233 234 index = next_subsys_index[level] 235 next_subsys_index[level] += 1 236 237 # Create a subsystem to contain the crossbar and caches, and 238 # any testers 239 subsys = SubSystem() 240 setattr(system, 'l%dsubsys%d' % (level, index), subsys) 241 242 # The levels are indexing backwards through the list 243 ntesters = testerspec[len(cachespec) - level] 244 245 # Scale the progress threshold as testers higher up in the tree 246 # (smaller level) get a smaller portion of the overall bandwidth, 247 # and also make the interval of packet injection longer for the 248 # testers closer to the memory (larger level) to prevent them 249 # hogging all the bandwidth 250 limit = (len(cachespec) - level + 1) * 100000000 251 testers = [proto_tester(interval = 10 * (level * level + 1), 252 progress_check = limit) \ 253 for i in xrange(ntesters)] 254 if ntesters: 255 subsys.tester = testers 256 257 if level != 0: 258 # Create a crossbar and add it to the subsystem, note that 259 # we do this even with a single element on this level 260 xbar = L2XBar() 261 subsys.xbar = xbar 262 if next_cache: 263 xbar.master = next_cache.cpu_side 264 265 # Create and connect the caches, both the ones fanning out 266 # to create the tree, and the ones used to connect testers 267 # on this level 268 tree_caches = [prototypes[0]() for i in xrange(ncaches[0])] 269 tester_caches = [proto_l1() for i in xrange(ntesters)] 270 271 subsys.cache = tester_caches + tree_caches 272 for cache in tree_caches: 273 cache.mem_side = xbar.slave 274 make_cache_level(ncaches[1:], prototypes[1:], level - 1, cache) 275 for tester, cache in zip(testers, tester_caches): 276 tester.port = cache.cpu_side 277 cache.mem_side = xbar.slave 278 else: 279 if not next_cache: 280 print "Error: No next-level cache at top level" 281 sys.exit(1) 282 283 if ntesters > 1: 284 # Create a crossbar and add it to the subsystem 285 xbar = L2XBar() 286 subsys.xbar = xbar 287 xbar.master = next_cache.cpu_side 288 for tester in testers: 289 tester.port = xbar.slave 290 else: 291 # Single tester 292 testers[0].port = next_cache.cpu_side 293 294# Top level call to create the cache hierarchy, bottom up 295make_cache_level(cachespec, cache_proto, len(cachespec), None) 296 297# Connect the lowest level crossbar to the memory 298last_subsys = getattr(system, 'l%dsubsys0' % len(cachespec)) 299last_subsys.xbar.master = system.physmem.port 300 301root = Root(full_system = False, system = system) 302if options.atomic: 303 root.system.mem_mode = 'atomic' 304else: 305 root.system.mem_mode = 'timing' 306 307# The system port is never used in the tester so merely connect it 308# to avoid problems 309root.system.system_port = last_subsys.xbar.slave 310 311# Instantiate configuration 312m5.instantiate() 313 314# Simulate until program terminates 315exit_event = m5.simulate(options.maxtick) 316 317print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause() 318