memcheck.py revision 12564
112531Sandreas.sandberg@arm.com# Copyright (c) 2015-2016 ARM Limited 212531Sandreas.sandberg@arm.com# All rights reserved. 312531Sandreas.sandberg@arm.com# 412531Sandreas.sandberg@arm.com# The license below extends only to copyright in the software and shall 512531Sandreas.sandberg@arm.com# not be construed as granting a license to any other intellectual 612531Sandreas.sandberg@arm.com# property including but not limited to intellectual property relating 712531Sandreas.sandberg@arm.com# to a hardware implementation of the functionality of the software 812531Sandreas.sandberg@arm.com# licensed hereunder. You may use the software subject to the license 912531Sandreas.sandberg@arm.com# terms below provided that you ensure that this notice is replicated 1012531Sandreas.sandberg@arm.com# unmodified and in its entirety in all distributions of the software, 1112531Sandreas.sandberg@arm.com# modified or unmodified, in source code or in binary form. 1212531Sandreas.sandberg@arm.com# 1312531Sandreas.sandberg@arm.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 1412531Sandreas.sandberg@arm.com# All rights reserved. 1512531Sandreas.sandberg@arm.com# 1612531Sandreas.sandberg@arm.com# Redistribution and use in source and binary forms, with or without 1712531Sandreas.sandberg@arm.com# modification, are permitted provided that the following conditions are 1812531Sandreas.sandberg@arm.com# met: redistributions of source code must retain the above copyright 1912531Sandreas.sandberg@arm.com# notice, this list of conditions and the following disclaimer; 2012531Sandreas.sandberg@arm.com# redistributions in binary form must reproduce the above copyright 2112531Sandreas.sandberg@arm.com# notice, this list of conditions and the following disclaimer in the 2212531Sandreas.sandberg@arm.com# documentation and/or other materials provided with the distribution; 2312531Sandreas.sandberg@arm.com# neither the name of the copyright holders nor the names of its 2412531Sandreas.sandberg@arm.com# contributors may be used to endorse or promote products derived from 2512531Sandreas.sandberg@arm.com# this software without specific prior written permission. 2612531Sandreas.sandberg@arm.com# 2712531Sandreas.sandberg@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2812531Sandreas.sandberg@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2912531Sandreas.sandberg@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3012531Sandreas.sandberg@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3112531Sandreas.sandberg@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3212531Sandreas.sandberg@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3312531Sandreas.sandberg@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3412531Sandreas.sandberg@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3512531Sandreas.sandberg@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3612531Sandreas.sandberg@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3712531Sandreas.sandberg@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3812531Sandreas.sandberg@arm.com# 3912531Sandreas.sandberg@arm.com# Authors: Ron Dreslinski 4012531Sandreas.sandberg@arm.com# Andreas Hansson 4112531Sandreas.sandberg@arm.com 4212531Sandreas.sandberg@arm.comfrom __future__ import print_function 4312531Sandreas.sandberg@arm.com 4412531Sandreas.sandberg@arm.comimport optparse 4512531Sandreas.sandberg@arm.comimport random 4612531Sandreas.sandberg@arm.comimport sys 4712531Sandreas.sandberg@arm.com 4812531Sandreas.sandberg@arm.comimport m5 4912531Sandreas.sandberg@arm.comfrom m5.objects import * 5012531Sandreas.sandberg@arm.com 5112531Sandreas.sandberg@arm.comparser = optparse.OptionParser() 5212531Sandreas.sandberg@arm.com 5312531Sandreas.sandberg@arm.comparser.add_option("-a", "--atomic", action="store_true", 5412531Sandreas.sandberg@arm.com help="Use atomic (non-timing) mode") 5512531Sandreas.sandberg@arm.comparser.add_option("-b", "--blocking", action="store_true", 5612531Sandreas.sandberg@arm.com help="Use blocking caches") 5712531Sandreas.sandberg@arm.comparser.add_option("-m", "--maxtick", type="int", default=m5.MaxTick, 5812531Sandreas.sandberg@arm.com metavar="T", 5912531Sandreas.sandberg@arm.com help="Stop after T ticks") 6012531Sandreas.sandberg@arm.comparser.add_option("-p", "--prefetchers", action="store_true", 6112531Sandreas.sandberg@arm.com help="Use prefetchers") 6212531Sandreas.sandberg@arm.comparser.add_option("-s", "--stridepref", action="store_true", 6312531Sandreas.sandberg@arm.com help="Use strided prefetchers") 6412531Sandreas.sandberg@arm.com 6512531Sandreas.sandberg@arm.com# This example script has a lot in common with the memtest.py in that 6612531Sandreas.sandberg@arm.com# it is designed to stress tests the memory system. However, this 6712531Sandreas.sandberg@arm.com# script uses oblivious traffic generators to create the stimuli, and 6812531Sandreas.sandberg@arm.com# couples them with memcheckers to verify that the data read matches 6912531Sandreas.sandberg@arm.com# the allowed outcomes. Just like memtest.py, the traffic generators 7012531Sandreas.sandberg@arm.com# and checkers are placed in a tree topology. At the bottom of the 7112531Sandreas.sandberg@arm.com# tree is a shared memory, and then at each level a number of 7212531Sandreas.sandberg@arm.com# generators and checkers are attached, along with a number of caches 7312531Sandreas.sandberg@arm.com# that them selves fan out to subtrees of generators and caches. Thus, 7412531Sandreas.sandberg@arm.com# it is possible to create a system with arbitrarily deep cache 7512531Sandreas.sandberg@arm.com# hierarchies, sharing or no sharing of caches, and generators not 7612531Sandreas.sandberg@arm.com# only at the L1s, but also at the L2s, L3s etc. 7712531Sandreas.sandberg@arm.com# 7812531Sandreas.sandberg@arm.com# The tree specification consists of two colon-separated lists of one 7912699Sandreas.sandberg@arm.com# or more integers, one for the caches, and one for the 8012531Sandreas.sandberg@arm.com# testers/generators. The first integer is the number of 8112531Sandreas.sandberg@arm.com# caches/testers closest to main memory. Each cache then fans out to a 8212531Sandreas.sandberg@arm.com# subtree. The last integer in the list is the number of 8312531Sandreas.sandberg@arm.com# caches/testers associated with the uppermost level of memory. The 8412531Sandreas.sandberg@arm.com# other integers (if any) specify the number of caches/testers 8512531Sandreas.sandberg@arm.com# connected at each level of the crossbar hierarchy. The tester string 8612531Sandreas.sandberg@arm.com# should have one element more than the cache string as there should 8712531Sandreas.sandberg@arm.com# always be testers attached to the uppermost caches. 8812531Sandreas.sandberg@arm.com# 8912531Sandreas.sandberg@arm.com# Since this script tests actual sharing, there is also a possibility 9012531Sandreas.sandberg@arm.com# to stress prefetching and the interaction between prefetchers and 9112531Sandreas.sandberg@arm.com# caches. The traffic generators switch between random address streams 9212531Sandreas.sandberg@arm.com# and linear address streams to ensure that the prefetchers will 9312531Sandreas.sandberg@arm.com# trigger. By default prefetchers are off. 9412531Sandreas.sandberg@arm.com 9512531Sandreas.sandberg@arm.comparser.add_option("-c", "--caches", type="string", default="3:2", 9612531Sandreas.sandberg@arm.com help="Colon-separated cache hierarchy specification, " 9712531Sandreas.sandberg@arm.com "see script comments for details " 9812531Sandreas.sandberg@arm.com "[default: %default]") 9912531Sandreas.sandberg@arm.comparser.add_option("-t", "--testers", type="string", default="1:0:2", 10012531Sandreas.sandberg@arm.com help="Colon-separated tester hierarchy specification, " 10112531Sandreas.sandberg@arm.com "see script comments for details " 10212531Sandreas.sandberg@arm.com "[default: %default]") 10312531Sandreas.sandberg@arm.comparser.add_option("-r", "--random", action="store_true", 10412531Sandreas.sandberg@arm.com help="Generate a random tree topology") 10512531Sandreas.sandberg@arm.comparser.add_option("--sys-clock", action="store", type="string", 10612531Sandreas.sandberg@arm.com default='1GHz', 10712531Sandreas.sandberg@arm.com help = """Top-level clock for blocks running at system 10812531Sandreas.sandberg@arm.com speed""") 10912531Sandreas.sandberg@arm.com 11012531Sandreas.sandberg@arm.com(options, args) = parser.parse_args() 11112531Sandreas.sandberg@arm.com 11212531Sandreas.sandberg@arm.comif args: 11312531Sandreas.sandberg@arm.com print("Error: script doesn't take any positional arguments") 11412531Sandreas.sandberg@arm.com sys.exit(1) 11512531Sandreas.sandberg@arm.com 11612531Sandreas.sandberg@arm.com# Start by parsing the command line options and do some basic sanity 11712531Sandreas.sandberg@arm.com# checking 11812531Sandreas.sandberg@arm.comif options.random: 11912531Sandreas.sandberg@arm.com # Generate a tree with a valid number of testers 12012531Sandreas.sandberg@arm.com tree_depth = random.randint(1, 4) 12112531Sandreas.sandberg@arm.com cachespec = [random.randint(1, 3) for i in range(tree_depth)] 12212531Sandreas.sandberg@arm.com testerspec = [random.randint(1, 3) for i in range(tree_depth + 1)] 12312531Sandreas.sandberg@arm.com print("Generated random tree -c", ':'.join(map(str, cachespec)), 12412698Sandreas.sandberg@arm.com "-t", ':'.join(map(str, testerspec))) 12512698Sandreas.sandberg@arm.comelse: 12612698Sandreas.sandberg@arm.com try: 12712698Sandreas.sandberg@arm.com cachespec = [int(x) for x in options.caches.split(':')] 12812698Sandreas.sandberg@arm.com testerspec = [int(x) for x in options.testers.split(':')] 12912698Sandreas.sandberg@arm.com except: 13012698Sandreas.sandberg@arm.com print("Error: Unable to parse caches or testers option") 13112698Sandreas.sandberg@arm.com sys.exit(1) 13212698Sandreas.sandberg@arm.com 13312531Sandreas.sandberg@arm.com if len(cachespec) < 1: 13412531Sandreas.sandberg@arm.com print("Error: Must have at least one level of caches") 13512531Sandreas.sandberg@arm.com sys.exit(1) 13612531Sandreas.sandberg@arm.com 13712531Sandreas.sandberg@arm.com if len(cachespec) != len(testerspec) - 1: 13812531Sandreas.sandberg@arm.com print("Error: Testers must have one element more than caches") 13912531Sandreas.sandberg@arm.com sys.exit(1) 14012698Sandreas.sandberg@arm.com 14112698Sandreas.sandberg@arm.com if testerspec[-1] == 0: 14212698Sandreas.sandberg@arm.com print("Error: Must have testers at the uppermost level") 14312698Sandreas.sandberg@arm.com sys.exit(1) 14412698Sandreas.sandberg@arm.com 14512531Sandreas.sandberg@arm.com for t in testerspec: 14612531Sandreas.sandberg@arm.com if t < 0: 14712531Sandreas.sandberg@arm.com print("Error: Cannot have a negative number of testers") 14812531Sandreas.sandberg@arm.com sys.exit(1) 14912531Sandreas.sandberg@arm.com 15012531Sandreas.sandberg@arm.com for c in cachespec: 15112531Sandreas.sandberg@arm.com if c < 1: 15212531Sandreas.sandberg@arm.com print("Error: Must have 1 or more caches at each level") 15312531Sandreas.sandberg@arm.com sys.exit(1) 15412531Sandreas.sandberg@arm.com 15512531Sandreas.sandberg@arm.com# Determine the tester multiplier for each level as the string 15612531Sandreas.sandberg@arm.com# elements are per subsystem and it fans out 15712531Sandreas.sandberg@arm.commultiplier = [1] 15812531Sandreas.sandberg@arm.comfor c in cachespec: 15912531Sandreas.sandberg@arm.com if c < 1: 16012531Sandreas.sandberg@arm.com print("Error: Must have at least one cache per level") 16112531Sandreas.sandberg@arm.com multiplier.append(multiplier[-1] * c) 16212531Sandreas.sandberg@arm.com 16312531Sandreas.sandberg@arm.comnumtesters = 0 16412531Sandreas.sandberg@arm.comfor t, m in zip(testerspec, multiplier): 16512531Sandreas.sandberg@arm.com numtesters += t * m 16612531Sandreas.sandberg@arm.com 16712531Sandreas.sandberg@arm.com# Define a prototype L1 cache that we scale for all successive levels 16812531Sandreas.sandberg@arm.comproto_l1 = Cache(size = '32kB', assoc = 4, 16912531Sandreas.sandberg@arm.com tag_latency = 1, data_latency = 1, response_latency = 1, 17012531Sandreas.sandberg@arm.com tgts_per_mshr = 8) 17112531Sandreas.sandberg@arm.com 17212531Sandreas.sandberg@arm.comif options.blocking: 17312533Sandreas.sandberg@arm.com proto_l1.mshrs = 1 17412531Sandreas.sandberg@arm.comelse: 17512531Sandreas.sandberg@arm.com proto_l1.mshrs = 4 17612531Sandreas.sandberg@arm.com 17712531Sandreas.sandberg@arm.comif options.prefetchers: 17812531Sandreas.sandberg@arm.com proto_l1.prefetcher = TaggedPrefetcher() 17913893Sgabeblack@google.comelif options.stridepref: 18012531Sandreas.sandberg@arm.com proto_l1.prefetcher = StridePrefetcher() 18112531Sandreas.sandberg@arm.com 18212531Sandreas.sandberg@arm.comcache_proto = [proto_l1] 18312531Sandreas.sandberg@arm.com 18412531Sandreas.sandberg@arm.com# Now add additional cache levels (if any) by scaling L1 params, the 18512531Sandreas.sandberg@arm.com# first element is Ln, and the last element L1 18612531Sandreas.sandberg@arm.comfor scale in cachespec[:-1]: 18712531Sandreas.sandberg@arm.com # Clone previous level and update params 18812531Sandreas.sandberg@arm.com prev = cache_proto[0] 18912531Sandreas.sandberg@arm.com next = prev() 19012531Sandreas.sandberg@arm.com next.size = prev.size * scale 19112531Sandreas.sandberg@arm.com next.tag_latency = prev.tag_latency * 10 19212531Sandreas.sandberg@arm.com next.data_latency = prev.data_latency * 10 19312531Sandreas.sandberg@arm.com next.response_latency = prev.response_latency * 10 19412531Sandreas.sandberg@arm.com next.assoc = prev.assoc * scale 19512531Sandreas.sandberg@arm.com next.mshrs = prev.mshrs * scale 19612531Sandreas.sandberg@arm.com cache_proto.insert(0, next) 19712531Sandreas.sandberg@arm.com 19812531Sandreas.sandberg@arm.com# Create a config to be used by all the traffic generators 19912531Sandreas.sandberg@arm.comcfg_file_name = "configs/example/memcheck.cfg" 20012531Sandreas.sandberg@arm.comcfg_file = open(cfg_file_name, 'w') 20112531Sandreas.sandberg@arm.com 20212531Sandreas.sandberg@arm.com# Three states, with random, linear and idle behaviours. The random 20312531Sandreas.sandberg@arm.com# and linear states access memory in the range [0 : 16 Mbyte] with 8 20412531Sandreas.sandberg@arm.com# byte and 64 byte accesses respectively. 20512531Sandreas.sandberg@arm.comcfg_file.write("STATE 0 10000000 RANDOM 65 0 16777216 8 50000 150000 0\n") 20612531Sandreas.sandberg@arm.comcfg_file.write("STATE 1 10000000 LINEAR 65 0 16777216 64 50000 150000 0\n") 20712531Sandreas.sandberg@arm.comcfg_file.write("STATE 2 10000000 IDLE\n") 20812533Sandreas.sandberg@arm.comcfg_file.write("INIT 0\n") 20912531Sandreas.sandberg@arm.comcfg_file.write("TRANSITION 0 1 0.5\n") 21012531Sandreas.sandberg@arm.comcfg_file.write("TRANSITION 0 2 0.5\n") 21112531Sandreas.sandberg@arm.comcfg_file.write("TRANSITION 1 0 0.5\n") 21212531Sandreas.sandberg@arm.comcfg_file.write("TRANSITION 1 2 0.5\n") 21312531Sandreas.sandberg@arm.comcfg_file.write("TRANSITION 2 0 0.5\n") 21413893Sgabeblack@google.comcfg_file.write("TRANSITION 2 1 0.5\n") 21512531Sandreas.sandberg@arm.comcfg_file.close() 21612531Sandreas.sandberg@arm.com 21712531Sandreas.sandberg@arm.com# Make a prototype for the tester to be used throughout 21812531Sandreas.sandberg@arm.comproto_tester = TrafficGen(config_file = cfg_file_name) 21912531Sandreas.sandberg@arm.com 22012531Sandreas.sandberg@arm.com# Set up the system along with a DRAM controller 22112531Sandreas.sandberg@arm.comsystem = System(physmem = DDR3_1600_8x8()) 22212531Sandreas.sandberg@arm.com 22312531Sandreas.sandberg@arm.comsystem.voltage_domain = VoltageDomain(voltage = '1V') 22412531Sandreas.sandberg@arm.com 22512531Sandreas.sandberg@arm.comsystem.clk_domain = SrcClockDomain(clock = options.sys_clock, 22612531Sandreas.sandberg@arm.com voltage_domain = system.voltage_domain) 22712531Sandreas.sandberg@arm.com 22812531Sandreas.sandberg@arm.comsystem.memchecker = MemChecker() 22912531Sandreas.sandberg@arm.com 23012531Sandreas.sandberg@arm.com# For each level, track the next subsys index to use 23112531Sandreas.sandberg@arm.comnext_subsys_index = [0] * (len(cachespec) + 1) 23212531Sandreas.sandberg@arm.com 23312531Sandreas.sandberg@arm.com# Recursive function to create a sub-tree of the cache and tester 23412531Sandreas.sandberg@arm.com# hierarchy 23512531Sandreas.sandberg@arm.comdef make_cache_level(ncaches, prototypes, level, next_cache): 23612531Sandreas.sandberg@arm.com global next_subsys_index, proto_l1, testerspec, proto_tester 23712531Sandreas.sandberg@arm.com 23812531Sandreas.sandberg@arm.com index = next_subsys_index[level] 23912531Sandreas.sandberg@arm.com next_subsys_index[level] += 1 24012531Sandreas.sandberg@arm.com 24112531Sandreas.sandberg@arm.com # Create a subsystem to contain the crossbar and caches, and 24212531Sandreas.sandberg@arm.com # any testers 24312531Sandreas.sandberg@arm.com subsys = SubSystem() 24412531Sandreas.sandberg@arm.com setattr(system, 'l%dsubsys%d' % (level, index), subsys) 24512531Sandreas.sandberg@arm.com 24612531Sandreas.sandberg@arm.com # The levels are indexing backwards through the list 24712531Sandreas.sandberg@arm.com ntesters = testerspec[len(cachespec) - level] 24812531Sandreas.sandberg@arm.com 24912531Sandreas.sandberg@arm.com testers = [proto_tester() for i in xrange(ntesters)] 25012531Sandreas.sandberg@arm.com checkers = [MemCheckerMonitor(memchecker = system.memchecker) \ 25112531Sandreas.sandberg@arm.com for i in xrange(ntesters)] 25212533Sandreas.sandberg@arm.com if ntesters: 25312533Sandreas.sandberg@arm.com subsys.tester = testers 25412533Sandreas.sandberg@arm.com subsys.checkers = checkers 25512533Sandreas.sandberg@arm.com 25612533Sandreas.sandberg@arm.com if level != 0: 25712533Sandreas.sandberg@arm.com # Create a crossbar and add it to the subsystem, note that 25812533Sandreas.sandberg@arm.com # we do this even with a single element on this level 25912533Sandreas.sandberg@arm.com xbar = L2XBar(width = 32) 26012533Sandreas.sandberg@arm.com subsys.xbar = xbar 26112533Sandreas.sandberg@arm.com if next_cache: 26212533Sandreas.sandberg@arm.com xbar.master = next_cache.cpu_side 26312533Sandreas.sandberg@arm.com 26412533Sandreas.sandberg@arm.com # Create and connect the caches, both the ones fanning out 26512533Sandreas.sandberg@arm.com # to create the tree, and the ones used to connect testers 26612533Sandreas.sandberg@arm.com # on this level 26712533Sandreas.sandberg@arm.com tree_caches = [prototypes[0]() for i in xrange(ncaches[0])] 26812533Sandreas.sandberg@arm.com tester_caches = [proto_l1() for i in xrange(ntesters)] 26912531Sandreas.sandberg@arm.com 27012531Sandreas.sandberg@arm.com subsys.cache = tester_caches + tree_caches 27112531Sandreas.sandberg@arm.com for cache in tree_caches: 27212531Sandreas.sandberg@arm.com cache.mem_side = xbar.slave 27312531Sandreas.sandberg@arm.com make_cache_level(ncaches[1:], prototypes[1:], level - 1, cache) 27412531Sandreas.sandberg@arm.com for tester, checker, cache in zip(testers, checkers, tester_caches): 27512533Sandreas.sandberg@arm.com tester.port = checker.slave 27612531Sandreas.sandberg@arm.com checker.master = cache.cpu_side 27712531Sandreas.sandberg@arm.com cache.mem_side = xbar.slave 27812531Sandreas.sandberg@arm.com else: 27912531Sandreas.sandberg@arm.com if not next_cache: 28012531Sandreas.sandberg@arm.com print("Error: No next-level cache at top level") 28112531Sandreas.sandberg@arm.com sys.exit(1) 28212531Sandreas.sandberg@arm.com 28312531Sandreas.sandberg@arm.com if ntesters > 1: 28412531Sandreas.sandberg@arm.com # Create a crossbar and add it to the subsystem 28512531Sandreas.sandberg@arm.com xbar = L2XBar(width = 32) 28612531Sandreas.sandberg@arm.com subsys.xbar = xbar 28712531Sandreas.sandberg@arm.com xbar.master = next_cache.cpu_side 28812531Sandreas.sandberg@arm.com for tester, checker in zip(testers, checkers): 28912531Sandreas.sandberg@arm.com tester.port = checker.slave 29012531Sandreas.sandberg@arm.com checker.master = xbar.slave 29112531Sandreas.sandberg@arm.com else: 29212531Sandreas.sandberg@arm.com # Single tester 29312531Sandreas.sandberg@arm.com testers[0].port = checkers[0].slave 29412531Sandreas.sandberg@arm.com checkers[0].master = next_cache.cpu_side 29512531Sandreas.sandberg@arm.com 29612531Sandreas.sandberg@arm.com# Top level call to create the cache hierarchy, bottom up 29712531Sandreas.sandberg@arm.commake_cache_level(cachespec, cache_proto, len(cachespec), None) 29812531Sandreas.sandberg@arm.com 29912531Sandreas.sandberg@arm.com# Connect the lowest level crossbar to the memory 30012531Sandreas.sandberg@arm.comlast_subsys = getattr(system, 'l%dsubsys0' % len(cachespec)) 30112531Sandreas.sandberg@arm.comlast_subsys.xbar.master = system.physmem.port 30212531Sandreas.sandberg@arm.comlast_subsys.xbar.point_of_coherency = True 30312531Sandreas.sandberg@arm.com 30412531Sandreas.sandberg@arm.comroot = Root(full_system = False, system = system) 30512531Sandreas.sandberg@arm.comif options.atomic: 30612531Sandreas.sandberg@arm.com root.system.mem_mode = 'atomic' 30712531Sandreas.sandberg@arm.comelse: 30812531Sandreas.sandberg@arm.com root.system.mem_mode = 'timing' 30912531Sandreas.sandberg@arm.com 31012531Sandreas.sandberg@arm.com# The system port is never used in the tester so merely connect it 31112531Sandreas.sandberg@arm.com# to avoid problems 31212531Sandreas.sandberg@arm.comroot.system.system_port = last_subsys.xbar.slave 31312531Sandreas.sandberg@arm.com 31412531Sandreas.sandberg@arm.com# Instantiate configuration 31512531Sandreas.sandberg@arm.comm5.instantiate() 31612531Sandreas.sandberg@arm.com 31712531Sandreas.sandberg@arm.com# Simulate until program terminates 31812531Sandreas.sandberg@arm.comexit_event = m5.simulate(options.maxtick) 31912531Sandreas.sandberg@arm.com 32012531Sandreas.sandberg@arm.comprint('Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()) 32112531Sandreas.sandberg@arm.com