memcheck.py revision 12564
1# Copyright (c) 2015-2016 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2006-2007 The Regents of The University of Michigan 14# All rights reserved. 15# 16# Redistribution and use in source and binary forms, with or without 17# modification, are permitted provided that the following conditions are 18# met: redistributions of source code must retain the above copyright 19# notice, this list of conditions and the following disclaimer; 20# redistributions in binary form must reproduce the above copyright 21# notice, this list of conditions and the following disclaimer in the 22# documentation and/or other materials provided with the distribution; 23# neither the name of the copyright holders nor the names of its 24# contributors may be used to endorse or promote products derived from 25# this software without specific prior written permission. 26# 27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Ron Dreslinski 40# Andreas Hansson 41 42from __future__ import print_function 43 44import optparse 45import random 46import sys 47 48import m5 49from m5.objects import * 50 51parser = optparse.OptionParser() 52 53parser.add_option("-a", "--atomic", action="store_true", 54 help="Use atomic (non-timing) mode") 55parser.add_option("-b", "--blocking", action="store_true", 56 help="Use blocking caches") 57parser.add_option("-m", "--maxtick", type="int", default=m5.MaxTick, 58 metavar="T", 59 help="Stop after T ticks") 60parser.add_option("-p", "--prefetchers", action="store_true", 61 help="Use prefetchers") 62parser.add_option("-s", "--stridepref", action="store_true", 63 help="Use strided prefetchers") 64 65# This example script has a lot in common with the memtest.py in that 66# it is designed to stress tests the memory system. However, this 67# script uses oblivious traffic generators to create the stimuli, and 68# couples them with memcheckers to verify that the data read matches 69# the allowed outcomes. Just like memtest.py, the traffic generators 70# and checkers are placed in a tree topology. At the bottom of the 71# tree is a shared memory, and then at each level a number of 72# generators and checkers are attached, along with a number of caches 73# that them selves fan out to subtrees of generators and caches. Thus, 74# it is possible to create a system with arbitrarily deep cache 75# hierarchies, sharing or no sharing of caches, and generators not 76# only at the L1s, but also at the L2s, L3s etc. 77# 78# The tree specification consists of two colon-separated lists of one 79# or more integers, one for the caches, and one for the 80# testers/generators. The first integer is the number of 81# caches/testers closest to main memory. Each cache then fans out to a 82# subtree. The last integer in the list is the number of 83# caches/testers associated with the uppermost level of memory. The 84# other integers (if any) specify the number of caches/testers 85# connected at each level of the crossbar hierarchy. The tester string 86# should have one element more than the cache string as there should 87# always be testers attached to the uppermost caches. 88# 89# Since this script tests actual sharing, there is also a possibility 90# to stress prefetching and the interaction between prefetchers and 91# caches. The traffic generators switch between random address streams 92# and linear address streams to ensure that the prefetchers will 93# trigger. By default prefetchers are off. 94 95parser.add_option("-c", "--caches", type="string", default="3:2", 96 help="Colon-separated cache hierarchy specification, " 97 "see script comments for details " 98 "[default: %default]") 99parser.add_option("-t", "--testers", type="string", default="1:0:2", 100 help="Colon-separated tester hierarchy specification, " 101 "see script comments for details " 102 "[default: %default]") 103parser.add_option("-r", "--random", action="store_true", 104 help="Generate a random tree topology") 105parser.add_option("--sys-clock", action="store", type="string", 106 default='1GHz', 107 help = """Top-level clock for blocks running at system 108 speed""") 109 110(options, args) = parser.parse_args() 111 112if args: 113 print("Error: script doesn't take any positional arguments") 114 sys.exit(1) 115 116# Start by parsing the command line options and do some basic sanity 117# checking 118if options.random: 119 # Generate a tree with a valid number of testers 120 tree_depth = random.randint(1, 4) 121 cachespec = [random.randint(1, 3) for i in range(tree_depth)] 122 testerspec = [random.randint(1, 3) for i in range(tree_depth + 1)] 123 print("Generated random tree -c", ':'.join(map(str, cachespec)), 124 "-t", ':'.join(map(str, testerspec))) 125else: 126 try: 127 cachespec = [int(x) for x in options.caches.split(':')] 128 testerspec = [int(x) for x in options.testers.split(':')] 129 except: 130 print("Error: Unable to parse caches or testers option") 131 sys.exit(1) 132 133 if len(cachespec) < 1: 134 print("Error: Must have at least one level of caches") 135 sys.exit(1) 136 137 if len(cachespec) != len(testerspec) - 1: 138 print("Error: Testers must have one element more than caches") 139 sys.exit(1) 140 141 if testerspec[-1] == 0: 142 print("Error: Must have testers at the uppermost level") 143 sys.exit(1) 144 145 for t in testerspec: 146 if t < 0: 147 print("Error: Cannot have a negative number of testers") 148 sys.exit(1) 149 150 for c in cachespec: 151 if c < 1: 152 print("Error: Must have 1 or more caches at each level") 153 sys.exit(1) 154 155# Determine the tester multiplier for each level as the string 156# elements are per subsystem and it fans out 157multiplier = [1] 158for c in cachespec: 159 if c < 1: 160 print("Error: Must have at least one cache per level") 161 multiplier.append(multiplier[-1] * c) 162 163numtesters = 0 164for t, m in zip(testerspec, multiplier): 165 numtesters += t * m 166 167# Define a prototype L1 cache that we scale for all successive levels 168proto_l1 = Cache(size = '32kB', assoc = 4, 169 tag_latency = 1, data_latency = 1, response_latency = 1, 170 tgts_per_mshr = 8) 171 172if options.blocking: 173 proto_l1.mshrs = 1 174else: 175 proto_l1.mshrs = 4 176 177if options.prefetchers: 178 proto_l1.prefetcher = TaggedPrefetcher() 179elif options.stridepref: 180 proto_l1.prefetcher = StridePrefetcher() 181 182cache_proto = [proto_l1] 183 184# Now add additional cache levels (if any) by scaling L1 params, the 185# first element is Ln, and the last element L1 186for scale in cachespec[:-1]: 187 # Clone previous level and update params 188 prev = cache_proto[0] 189 next = prev() 190 next.size = prev.size * scale 191 next.tag_latency = prev.tag_latency * 10 192 next.data_latency = prev.data_latency * 10 193 next.response_latency = prev.response_latency * 10 194 next.assoc = prev.assoc * scale 195 next.mshrs = prev.mshrs * scale 196 cache_proto.insert(0, next) 197 198# Create a config to be used by all the traffic generators 199cfg_file_name = "configs/example/memcheck.cfg" 200cfg_file = open(cfg_file_name, 'w') 201 202# Three states, with random, linear and idle behaviours. The random 203# and linear states access memory in the range [0 : 16 Mbyte] with 8 204# byte and 64 byte accesses respectively. 205cfg_file.write("STATE 0 10000000 RANDOM 65 0 16777216 8 50000 150000 0\n") 206cfg_file.write("STATE 1 10000000 LINEAR 65 0 16777216 64 50000 150000 0\n") 207cfg_file.write("STATE 2 10000000 IDLE\n") 208cfg_file.write("INIT 0\n") 209cfg_file.write("TRANSITION 0 1 0.5\n") 210cfg_file.write("TRANSITION 0 2 0.5\n") 211cfg_file.write("TRANSITION 1 0 0.5\n") 212cfg_file.write("TRANSITION 1 2 0.5\n") 213cfg_file.write("TRANSITION 2 0 0.5\n") 214cfg_file.write("TRANSITION 2 1 0.5\n") 215cfg_file.close() 216 217# Make a prototype for the tester to be used throughout 218proto_tester = TrafficGen(config_file = cfg_file_name) 219 220# Set up the system along with a DRAM controller 221system = System(physmem = DDR3_1600_8x8()) 222 223system.voltage_domain = VoltageDomain(voltage = '1V') 224 225system.clk_domain = SrcClockDomain(clock = options.sys_clock, 226 voltage_domain = system.voltage_domain) 227 228system.memchecker = MemChecker() 229 230# For each level, track the next subsys index to use 231next_subsys_index = [0] * (len(cachespec) + 1) 232 233# Recursive function to create a sub-tree of the cache and tester 234# hierarchy 235def make_cache_level(ncaches, prototypes, level, next_cache): 236 global next_subsys_index, proto_l1, testerspec, proto_tester 237 238 index = next_subsys_index[level] 239 next_subsys_index[level] += 1 240 241 # Create a subsystem to contain the crossbar and caches, and 242 # any testers 243 subsys = SubSystem() 244 setattr(system, 'l%dsubsys%d' % (level, index), subsys) 245 246 # The levels are indexing backwards through the list 247 ntesters = testerspec[len(cachespec) - level] 248 249 testers = [proto_tester() for i in xrange(ntesters)] 250 checkers = [MemCheckerMonitor(memchecker = system.memchecker) \ 251 for i in xrange(ntesters)] 252 if ntesters: 253 subsys.tester = testers 254 subsys.checkers = checkers 255 256 if level != 0: 257 # Create a crossbar and add it to the subsystem, note that 258 # we do this even with a single element on this level 259 xbar = L2XBar(width = 32) 260 subsys.xbar = xbar 261 if next_cache: 262 xbar.master = next_cache.cpu_side 263 264 # Create and connect the caches, both the ones fanning out 265 # to create the tree, and the ones used to connect testers 266 # on this level 267 tree_caches = [prototypes[0]() for i in xrange(ncaches[0])] 268 tester_caches = [proto_l1() for i in xrange(ntesters)] 269 270 subsys.cache = tester_caches + tree_caches 271 for cache in tree_caches: 272 cache.mem_side = xbar.slave 273 make_cache_level(ncaches[1:], prototypes[1:], level - 1, cache) 274 for tester, checker, cache in zip(testers, checkers, tester_caches): 275 tester.port = checker.slave 276 checker.master = cache.cpu_side 277 cache.mem_side = xbar.slave 278 else: 279 if not next_cache: 280 print("Error: No next-level cache at top level") 281 sys.exit(1) 282 283 if ntesters > 1: 284 # Create a crossbar and add it to the subsystem 285 xbar = L2XBar(width = 32) 286 subsys.xbar = xbar 287 xbar.master = next_cache.cpu_side 288 for tester, checker in zip(testers, checkers): 289 tester.port = checker.slave 290 checker.master = xbar.slave 291 else: 292 # Single tester 293 testers[0].port = checkers[0].slave 294 checkers[0].master = next_cache.cpu_side 295 296# Top level call to create the cache hierarchy, bottom up 297make_cache_level(cachespec, cache_proto, len(cachespec), None) 298 299# Connect the lowest level crossbar to the memory 300last_subsys = getattr(system, 'l%dsubsys0' % len(cachespec)) 301last_subsys.xbar.master = system.physmem.port 302last_subsys.xbar.point_of_coherency = True 303 304root = Root(full_system = False, system = system) 305if options.atomic: 306 root.system.mem_mode = 'atomic' 307else: 308 root.system.mem_mode = 'timing' 309 310# The system port is never used in the tester so merely connect it 311# to avoid problems 312root.system.system_port = last_subsys.xbar.slave 313 314# Instantiate configuration 315m5.instantiate() 316 317# Simulate until program terminates 318exit_event = m5.simulate(options.maxtick) 319 320print('Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()) 321