fs.py revision 8863
16654Snate@binkert.org# Copyright (c) 2010-2011 ARM Limited
26654Snate@binkert.org# All rights reserved.
35467Snate@binkert.org#
45467Snate@binkert.org# The license below extends only to copyright in the software and shall
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65467Snate@binkert.org# property including but not limited to intellectual property relating
75467Snate@binkert.org# to a hardware implementation of the functionality of the software
85467Snate@binkert.org# licensed hereunder.  You may use the software subject to the license
95467Snate@binkert.org# terms below provided that you ensure that this notice is replicated
105467Snate@binkert.org# unmodified and in its entirety in all distributions of the software,
115467Snate@binkert.org# modified or unmodified, in source code or in binary form.
125467Snate@binkert.org#
135467Snate@binkert.org# Copyright (c) 2006-2007 The Regents of The University of Michigan
145467Snate@binkert.org# All rights reserved.
155467Snate@binkert.org#
165467Snate@binkert.org# Redistribution and use in source and binary forms, with or without
175467Snate@binkert.org# modification, are permitted provided that the following conditions are
185467Snate@binkert.org# met: redistributions of source code must retain the above copyright
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205467Snate@binkert.org# redistributions in binary form must reproduce the above copyright
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255467Snate@binkert.org# this software without specific prior written permission.
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275467Snate@binkert.org# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
285467Snate@binkert.org# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
295467Snate@binkert.org# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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377459Snate@binkert.org# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
386502Snate@binkert.org#
395467Snate@binkert.org# Authors: Ali Saidi
406500Snate@binkert.org
416654Snate@binkert.orgimport optparse
425873Snate@binkert.orgimport os
436654Snate@binkert.orgimport sys
446654Snate@binkert.org
456654Snate@binkert.orgimport m5
466654Snate@binkert.orgfrom m5.defines import buildEnv
476654Snate@binkert.orgfrom m5.objects import *
486654Snate@binkert.orgfrom m5.util import addToPath, fatal
496654Snate@binkert.org
506654Snate@binkert.orgaddToPath('../common')
516654Snate@binkert.org
526654Snate@binkert.orgfrom FSConfig import *
536654Snate@binkert.orgfrom SysPaths import *
546654Snate@binkert.orgfrom Benchmarks import *
556654Snate@binkert.orgimport Simulation
566654Snate@binkert.orgimport CacheConfig
576654Snate@binkert.orgfrom Caches import *
586654Snate@binkert.org
596654Snate@binkert.org# Get paths we might need.  It's expected this file is in m5/configs/example.
606654Snate@binkert.orgconfig_path = os.path.dirname(os.path.abspath(__file__))
616654Snate@binkert.orgconfig_root = os.path.dirname(config_path)
626654Snate@binkert.org
636654Snate@binkert.orgparser = optparse.OptionParser()
646654Snate@binkert.org
656654Snate@binkert.org# Simulation options
666654Snate@binkert.orgparser.add_option("--timesync", action="store_true",
676654Snate@binkert.org        help="Prevent simulated time from getting ahead of real time")
686654Snate@binkert.org
696654Snate@binkert.org# System options
706654Snate@binkert.orgparser.add_option("--kernel", action="store", type="string")
716654Snate@binkert.orgparser.add_option("--script", action="store", type="string")
726654Snate@binkert.orgparser.add_option("--frame-capture", action="store_true",
736654Snate@binkert.org        help="Stores changed frame buffers from the VNC server to compressed "\
746654Snate@binkert.org        "files in the gem5 output directory")
756654Snate@binkert.org
766654Snate@binkert.orgif buildEnv['TARGET_ISA'] == "arm":
776654Snate@binkert.org    parser.add_option("--bare-metal", action="store_true",
786654Snate@binkert.org               help="Provide the raw system without the linux specific bits")
796654Snate@binkert.org    parser.add_option("--machine-type", action="store", type="choice",
806654Snate@binkert.org            choices=ArmMachineType.map.keys(), default="RealView_PBX")
816654Snate@binkert.org# Benchmark options
826654Snate@binkert.orgparser.add_option("--dual", action="store_true",
836654Snate@binkert.org                  help="Simulate two systems attached with an ethernet link")
846654Snate@binkert.orgparser.add_option("-b", "--benchmark", action="store", type="string",
856654Snate@binkert.org                  dest="benchmark",
866654Snate@binkert.org                  help="Specify the benchmark to run. Available benchmarks: %s"\
876654Snate@binkert.org                  % DefinedBenchmarks)
886654Snate@binkert.org
896654Snate@binkert.org# Metafile options
906654Snate@binkert.orgparser.add_option("--etherdump", action="store", type="string", dest="etherdump",
916654Snate@binkert.org                  help="Specify the filename to dump a pcap capture of the" \
926654Snate@binkert.org                  "ethernet traffic")
936654Snate@binkert.org
946654Snate@binkert.orgexecfile(os.path.join(config_root, "common", "Options.py"))
956654Snate@binkert.org
966654Snate@binkert.org(options, args) = parser.parse_args()
976654Snate@binkert.org
986654Snate@binkert.orgif args:
996654Snate@binkert.org    print "Error: script doesn't take any positional arguments"
1006654Snate@binkert.org    sys.exit(1)
1016654Snate@binkert.org
1026654Snate@binkert.org# driver system CPU is always simple... note this is an assignment of
1036654Snate@binkert.org# a class, not an instance.
1046654Snate@binkert.orgDriveCPUClass = AtomicSimpleCPU
1056654Snate@binkert.orgdrive_mem_mode = 'atomic'
1066654Snate@binkert.org
1076654Snate@binkert.org# system under test can be any CPU
1086654Snate@binkert.org(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
1096654Snate@binkert.org
1106654Snate@binkert.orgTestCPUClass.clock = '2GHz'
1116654Snate@binkert.orgDriveCPUClass.clock = '2GHz'
1126654Snate@binkert.org
1136654Snate@binkert.orgif options.benchmark:
1146654Snate@binkert.org    try:
1156654Snate@binkert.org        bm = Benchmarks[options.benchmark]
1166654Snate@binkert.org    except KeyError:
1176654Snate@binkert.org        print "Error benchmark %s has not been defined." % options.benchmark
1186654Snate@binkert.org        print "Valid benchmarks are: %s" % DefinedBenchmarks
1196654Snate@binkert.org        sys.exit(1)
1206654Snate@binkert.orgelse:
1216654Snate@binkert.org    if options.dual:
1226654Snate@binkert.org        bm = [SysConfig(), SysConfig()]
1236654Snate@binkert.org    else:
1246654Snate@binkert.org        bm = [SysConfig()]
1256654Snate@binkert.org
1266654Snate@binkert.orgnp = options.num_cpus
1276654Snate@binkert.org
1286654Snate@binkert.orgif buildEnv['TARGET_ISA'] == "alpha":
1296654Snate@binkert.org    test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0])
1306654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == "mips":
1316654Snate@binkert.org    test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0])
1326654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == "sparc":
1336654Snate@binkert.org    test_sys = makeSparcSystem(test_mem_mode, bm[0])
1346654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == "x86":
1356654Snate@binkert.org    test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0])
1366654Snate@binkert.org    setWorkCountOptions(test_sys, options)
1376654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == "arm":
1386654Snate@binkert.org    test_sys = makeArmSystem(test_mem_mode,
1396654Snate@binkert.org            options.machine_type, bm[0],
1406654Snate@binkert.org            bare_metal=options.bare_metal)
1416654Snate@binkert.org    setWorkCountOptions(test_sys, options)
1426654Snate@binkert.orgelse:
1436654Snate@binkert.org    fatal("incapable of building non-alpha or non-sparc full system!")
1446654Snate@binkert.org
1456654Snate@binkert.orgif options.kernel is not None:
1466654Snate@binkert.org    test_sys.kernel = binary(options.kernel)
1476654Snate@binkert.org
1486654Snate@binkert.orgif options.script is not None:
1496654Snate@binkert.org    test_sys.readfile = options.script
1506654Snate@binkert.org
1516654Snate@binkert.orgtest_sys.init_param = options.init_param
1526654Snate@binkert.org
1536654Snate@binkert.orgtest_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
1545873Snate@binkert.org
1555873Snate@binkert.orgCacheConfig.config_cache(options, test_sys)
1565873Snate@binkert.org
1575873Snate@binkert.orgif bm[0]:
1585873Snate@binkert.org    mem_size = bm[0].mem()
1595873Snate@binkert.orgelse:
1605873Snate@binkert.org    mem_size = SysConfig().mem()
1615873Snate@binkert.orgif options.caches or options.l2cache:
1625873Snate@binkert.org    test_sys.iocache = IOCache(addr_range=mem_size)
1635873Snate@binkert.org    test_sys.iocache.cpu_side = test_sys.iobus.master
1645873Snate@binkert.org    test_sys.iocache.mem_side = test_sys.membus.slave
1656654Snate@binkert.orgelse:
1666654Snate@binkert.org    test_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
1676654Snate@binkert.org                               ranges = [AddrRange(mem_size)])
1686654Snate@binkert.org    test_sys.iobridge.slave = test_sys.iobus.master
1696654Snate@binkert.org    test_sys.iobridge.master = test_sys.membus.slave
1706654Snate@binkert.org
1716654Snate@binkert.orgfor i in xrange(np):
1726654Snate@binkert.org    if options.fastmem:
1736654Snate@binkert.org        test_sys.cpu[i].physmem_port = test_sys.physmem.port
1746654Snate@binkert.org
1756654Snate@binkert.orgif buildEnv['TARGET_ISA'] == 'mips':
1766654Snate@binkert.org    setMipsOptions(TestCPUClass)
1776654Snate@binkert.org
1786654Snate@binkert.orgif len(bm) == 2:
1796654Snate@binkert.org    if buildEnv['TARGET_ISA'] == 'alpha':
1806654Snate@binkert.org        drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
1816654Snate@binkert.org    elif buildEnv['TARGET_ISA'] == 'mips':
1826654Snate@binkert.org        drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1])
1836654Snate@binkert.org    elif buildEnv['TARGET_ISA'] == 'sparc':
1846654Snate@binkert.org        drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
1856654Snate@binkert.org    elif buildEnv['TARGET_ISA'] == 'x86':
1866654Snate@binkert.org        drive_sys = makeX86System(drive_mem_mode, np, bm[1])
1876654Snate@binkert.org    elif buildEnv['TARGET_ISA'] == 'arm':
1886654Snate@binkert.org        drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1])
189
190    drive_sys.cpu = DriveCPUClass(cpu_id=0)
191    drive_sys.cpu.createInterruptController()
192    drive_sys.cpu.connectAllPorts(drive_sys.membus)
193    if options.fastmem:
194        drive_sys.cpu.physmem_port = drive_sys.physmem.port
195    if options.kernel is not None:
196        drive_sys.kernel = binary(options.kernel)
197    drive_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
198                               ranges = [AddrRange(bm[1].mem())])
199    drive_sys.iobridge.slave = drive_sys.iobus.master
200    drive_sys.iobridge.master = drive_sys.membus.slave
201
202    drive_sys.init_param = options.init_param
203    root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
204elif len(bm) == 1:
205    root = Root(full_system=True, system=test_sys)
206else:
207    print "Error I don't know how to create more than 2 systems."
208    sys.exit(1)
209
210if options.timesync:
211    root.time_sync_enable = True
212
213if options.frame_capture:
214    VncServer.frame_capture = True
215
216Simulation.run(options, root, test_sys, FutureClass)
217