fs.py revision 9836
19793Sakash.bagdia@arm.com# Copyright (c) 2010-2013 ARM Limited 27586SAli.Saidi@arm.com# All rights reserved. 37586SAli.Saidi@arm.com# 47586SAli.Saidi@arm.com# The license below extends only to copyright in the software and shall 57586SAli.Saidi@arm.com# not be construed as granting a license to any other intellectual 67586SAli.Saidi@arm.com# property including but not limited to intellectual property relating 77586SAli.Saidi@arm.com# to a hardware implementation of the functionality of the software 87586SAli.Saidi@arm.com# licensed hereunder. You may use the software subject to the license 97586SAli.Saidi@arm.com# terms below provided that you ensure that this notice is replicated 107586SAli.Saidi@arm.com# unmodified and in its entirety in all distributions of the software, 117586SAli.Saidi@arm.com# modified or unmodified, in source code or in binary form. 127586SAli.Saidi@arm.com# 133970Sgblack@eecs.umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 143005Sstever@eecs.umich.edu# All rights reserved. 153005Sstever@eecs.umich.edu# 163005Sstever@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 173005Sstever@eecs.umich.edu# modification, are permitted provided that the following conditions are 183005Sstever@eecs.umich.edu# met: redistributions of source code must retain the above copyright 193005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 203005Sstever@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 213005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 223005Sstever@eecs.umich.edu# documentation and/or other materials provided with the distribution; 233005Sstever@eecs.umich.edu# neither the name of the copyright holders nor the names of its 243005Sstever@eecs.umich.edu# contributors may be used to endorse or promote products derived from 253005Sstever@eecs.umich.edu# this software without specific prior written permission. 263005Sstever@eecs.umich.edu# 273005Sstever@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 283005Sstever@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 293005Sstever@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 303005Sstever@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 313005Sstever@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 323005Sstever@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 333005Sstever@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 343005Sstever@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 353005Sstever@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 363005Sstever@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 373005Sstever@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 383005Sstever@eecs.umich.edu# 393005Sstever@eecs.umich.edu# Authors: Ali Saidi 403005Sstever@eecs.umich.edu 416654Snate@binkert.orgimport optparse 426654Snate@binkert.orgimport sys 432889SN/A 442710SN/Aimport m5 456654Snate@binkert.orgfrom m5.defines import buildEnv 466654Snate@binkert.orgfrom m5.objects import * 476654Snate@binkert.orgfrom m5.util import addToPath, fatal 485457Ssaidi@eecs.umich.edu 496654Snate@binkert.orgaddToPath('../common') 506654Snate@binkert.org 512934SN/Afrom FSConfig import * 522549SN/Afrom SysPaths import * 532995SN/Afrom Benchmarks import * 543395Shsul@eecs.umich.eduimport Simulation 556981SLisa.Hsu@amd.comimport CacheConfig 569836Sandreas.hansson@arm.comimport MemConfig 573448Shsul@eecs.umich.edufrom Caches import * 588920Snilay@cs.wisc.eduimport Options 593444Sktlim@umich.edu 602889SN/Aparser = optparse.OptionParser() 618920Snilay@cs.wisc.eduOptions.addCommonOptions(parser) 628920Snilay@cs.wisc.eduOptions.addFSOptions(parser) 633322Shsul@eecs.umich.edu 642710SN/A(options, args) = parser.parse_args() 652710SN/A 662710SN/Aif args: 672710SN/A print "Error: script doesn't take any positional arguments" 682710SN/A sys.exit(1) 692710SN/A 703322Shsul@eecs.umich.edu# driver system CPU is always simple... note this is an assignment of 713304Sstever@eecs.umich.edu# a class, not an instance. 723322Shsul@eecs.umich.eduDriveCPUClass = AtomicSimpleCPU 733322Shsul@eecs.umich.edudrive_mem_mode = 'atomic' 743304Sstever@eecs.umich.edu 759653SAndreas.Sandberg@ARM.com# Check if KVM support has been enabled, we might need to do VM 769653SAndreas.Sandberg@ARM.com# configuration if that's the case. 779653SAndreas.Sandberg@ARM.comhave_kvm_support = 'BaseKvmCPU' in globals() 789653SAndreas.Sandberg@ARM.comdef is_kvm_cpu(cpu_class): 799653SAndreas.Sandberg@ARM.com return have_kvm_support and cpu_class != None and \ 809653SAndreas.Sandberg@ARM.com issubclass(cpu_class, BaseKvmCPU) 819653SAndreas.Sandberg@ARM.com 823481Shsul@eecs.umich.edu# system under test can be any CPU 833481Shsul@eecs.umich.edu(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 842566SN/A 859665Sandreas.hansson@arm.com# Match the memories with the CPUs, the driver system always simple, 869665Sandreas.hansson@arm.com# and based on the options for the test system 879665Sandreas.hansson@arm.comDriveMemClass = SimpleMemory 889665Sandreas.hansson@arm.comTestMemClass = Simulation.setMemClass(options) 899665Sandreas.hansson@arm.com 902995SN/Aif options.benchmark: 913304Sstever@eecs.umich.edu try: 923304Sstever@eecs.umich.edu bm = Benchmarks[options.benchmark] 933304Sstever@eecs.umich.edu except KeyError: 942995SN/A print "Error benchmark %s has not been defined." % options.benchmark 952995SN/A print "Valid benchmarks are: %s" % DefinedBenchmarks 962995SN/A sys.exit(1) 972917SN/Aelse: 982995SN/A if options.dual: 998956Sjayneel@cs.wisc.edu bm = [SysConfig(disk=options.disk_image, mem=options.mem_size), SysConfig(disk=options.disk_image, mem=options.mem_size)] 1002995SN/A else: 1018956Sjayneel@cs.wisc.edu bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)] 1023304Sstever@eecs.umich.edu 1036135Sgblack@eecs.umich.edunp = options.num_cpus 1046135Sgblack@eecs.umich.edu 1056654Snate@binkert.orgif buildEnv['TARGET_ISA'] == "alpha": 1069826Sandreas.hansson@arm.com test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0]) 1076654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == "mips": 1089826Sandreas.hansson@arm.com test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0]) 1096654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == "sparc": 1109826Sandreas.hansson@arm.com test_sys = makeSparcSystem(test_mem_mode, bm[0]) 1116654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == "x86": 1129826Sandreas.hansson@arm.com test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0]) 1137586SAli.Saidi@arm.comelif buildEnv['TARGET_ISA'] == "arm": 1149826Sandreas.hansson@arm.com test_sys = makeArmSystem(test_mem_mode, options.machine_type, bm[0], 1159826Sandreas.hansson@arm.com options.dtb_filename, 1169665Sandreas.hansson@arm.com bare_metal=options.bare_metal) 1173819Shsul@eecs.umich.eduelse: 1189059Snilay@cs.wisc.edu fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) 1193819Shsul@eecs.umich.edu 1209827Sakash.bagdia@arm.com# Create a top-level voltage domain 1219827Sakash.bagdia@arm.comtest_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 1229827Sakash.bagdia@arm.com 1239793Sakash.bagdia@arm.com# Create a source clock for the system and set the clock period 1249827Sakash.bagdia@arm.comtest_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, 1259827Sakash.bagdia@arm.com voltage_domain = test_sys.voltage_domain) 1269827Sakash.bagdia@arm.com 1279827Sakash.bagdia@arm.com# Create a CPU voltage domain 1289827Sakash.bagdia@arm.comtest_sys.cpu_voltage_domain = VoltageDomain() 1299793Sakash.bagdia@arm.com 1309793Sakash.bagdia@arm.com# Create a source clock for the CPUs and set the clock period 1319827Sakash.bagdia@arm.comtest_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 1329827Sakash.bagdia@arm.com voltage_domain = 1339827Sakash.bagdia@arm.com test_sys.cpu_voltage_domain) 1349790Sakash.bagdia@arm.com 1353873Sbinkertn@umich.eduif options.kernel is not None: 1363873Sbinkertn@umich.edu test_sys.kernel = binary(options.kernel) 1373873Sbinkertn@umich.edu 1383873Sbinkertn@umich.eduif options.script is not None: 1393873Sbinkertn@umich.edu test_sys.readfile = options.script 1403873Sbinkertn@umich.edu 1418659SAli.Saidi@ARM.comtest_sys.init_param = options.init_param 1428659SAli.Saidi@ARM.com 1439793Sakash.bagdia@arm.com# For now, assign all the CPUs to the same clock domain 1449793Sakash.bagdia@arm.comtest_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) 1459793Sakash.bagdia@arm.com for i in xrange(np)] 1463668Srdreslin@umich.edu 1479653SAndreas.Sandberg@ARM.comif is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass): 1489653SAndreas.Sandberg@ARM.com test_sys.vm = KvmVM() 1499653SAndreas.Sandberg@ARM.com 1506636Ssteve.reinhardt@amd.comif options.caches or options.l2cache: 1519788Sakash.bagdia@arm.com # By default the IOCache runs at the system clock 1529788Sakash.bagdia@arm.com test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges) 1538839Sandreas.hansson@arm.com test_sys.iocache.cpu_side = test_sys.iobus.master 1548839Sandreas.hansson@arm.com test_sys.iocache.mem_side = test_sys.membus.slave 1558713Sandreas.hansson@arm.comelse: 1569408Sandreas.hansson@arm.com test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) 1578839Sandreas.hansson@arm.com test_sys.iobridge.slave = test_sys.iobus.master 1588839Sandreas.hansson@arm.com test_sys.iobridge.master = test_sys.membus.slave 1595142Ssaidi@eecs.umich.edu 1608926Sandreas.hansson@arm.com# Sanity check 1619317Sandreas.hansson@arm.comif options.fastmem: 1629317Sandreas.hansson@arm.com if TestCPUClass != AtomicSimpleCPU: 1639317Sandreas.hansson@arm.com fatal("Fastmem can only be used with atomic CPU!") 1649317Sandreas.hansson@arm.com if (options.caches or options.l2cache): 1659317Sandreas.hansson@arm.com fatal("You cannot use fastmem in combination with caches!") 1668926Sandreas.hansson@arm.com 1673312Sstever@eecs.umich.edufor i in xrange(np): 1684968Sacolyte@umich.edu if options.fastmem: 1698926Sandreas.hansson@arm.com test_sys.cpu[i].fastmem = True 1708887Sgeoffrey.blake@arm.com if options.checker: 1718887Sgeoffrey.blake@arm.com test_sys.cpu[i].addCheckerCpu() 1729384SAndreas.Sandberg@arm.com test_sys.cpu[i].createThreads() 1738887Sgeoffrey.blake@arm.com 1748887Sgeoffrey.blake@arm.comCacheConfig.config_cache(options, test_sys) 1759836Sandreas.hansson@arm.comMemConfig.config_mem(options, test_sys) 1769826Sandreas.hansson@arm.com 1773005Sstever@eecs.umich.eduif len(bm) == 2: 1786654Snate@binkert.org if buildEnv['TARGET_ISA'] == 'alpha': 1799826Sandreas.hansson@arm.com drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1]) 1806654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'mips': 1819826Sandreas.hansson@arm.com drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1]) 1826654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'sparc': 1839826Sandreas.hansson@arm.com drive_sys = makeSparcSystem(drive_mem_mode, bm[1]) 1846654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'x86': 1859826Sandreas.hansson@arm.com drive_sys = makeX86System(drive_mem_mode, np, bm[1]) 1867586SAli.Saidi@arm.com elif buildEnv['TARGET_ISA'] == 'arm': 1879826Sandreas.hansson@arm.com drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1]) 1888661SAli.Saidi@ARM.com 1899827Sakash.bagdia@arm.com # Create a top-level voltage domain 1909827Sakash.bagdia@arm.com drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 1919827Sakash.bagdia@arm.com 1929793Sakash.bagdia@arm.com # Create a source clock for the system and set the clock period 1939793Sakash.bagdia@arm.com drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock) 1949790Sakash.bagdia@arm.com 1959827Sakash.bagdia@arm.com # Create a CPU voltage domain 1969827Sakash.bagdia@arm.com drive_sys.cpu_voltage_domain = VoltageDomain() 1979827Sakash.bagdia@arm.com 1989793Sakash.bagdia@arm.com # Create a source clock for the CPUs and set the clock period 1999827Sakash.bagdia@arm.com drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 2009827Sakash.bagdia@arm.com voltage_domain = 2019827Sakash.bagdia@arm.com drive_sys.cpu_voltage_domain) 2029793Sakash.bagdia@arm.com 2039793Sakash.bagdia@arm.com drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain, 2049793Sakash.bagdia@arm.com cpu_id=0) 2059384SAndreas.Sandberg@arm.com drive_sys.cpu.createThreads() 2068863Snilay@cs.wisc.edu drive_sys.cpu.createInterruptController() 2077876Sgblack@eecs.umich.edu drive_sys.cpu.connectAllPorts(drive_sys.membus) 2084968Sacolyte@umich.edu if options.fastmem: 2098926Sandreas.hansson@arm.com drive_sys.cpu.fastmem = True 2104837Ssaidi@eecs.umich.edu if options.kernel is not None: 2114837Ssaidi@eecs.umich.edu drive_sys.kernel = binary(options.kernel) 2129408Sandreas.hansson@arm.com 2139653SAndreas.Sandberg@ARM.com if is_kvm_cpu(DriveCPUClass): 2149653SAndreas.Sandberg@ARM.com drive_sys.vm = KvmVM() 2159653SAndreas.Sandberg@ARM.com 2169164Sandreas.hansson@arm.com drive_sys.iobridge = Bridge(delay='50ns', 2179408Sandreas.hansson@arm.com ranges = drive_sys.mem_ranges) 2188845Sandreas.hansson@arm.com drive_sys.iobridge.slave = drive_sys.iobus.master 2198845Sandreas.hansson@arm.com drive_sys.iobridge.master = drive_sys.membus.slave 2204837Ssaidi@eecs.umich.edu 2219826Sandreas.hansson@arm.com # Create the appropriate memory controllers and connect them to the 2229826Sandreas.hansson@arm.com # memory bus 2239835Sandreas.hansson@arm.com drive_sys.mem_ctrls = [DriveMemClass(range = r) 2249826Sandreas.hansson@arm.com for r in drive_sys.mem_ranges] 2259826Sandreas.hansson@arm.com for i in xrange(len(drive_sys.mem_ctrls)): 2269826Sandreas.hansson@arm.com drive_sys.mem_ctrls[i].port = drive_sys.membus.master 2279826Sandreas.hansson@arm.com 2288659SAli.Saidi@ARM.com drive_sys.init_param = options.init_param 2298801Sgblack@eecs.umich.edu root = makeDualRoot(True, test_sys, drive_sys, options.etherdump) 2303005Sstever@eecs.umich.eduelif len(bm) == 1: 2318801Sgblack@eecs.umich.edu root = Root(full_system=True, system=test_sys) 2323005Sstever@eecs.umich.eduelse: 2333005Sstever@eecs.umich.edu print "Error I don't know how to create more than 2 systems." 2343005Sstever@eecs.umich.edu sys.exit(1) 2352566SN/A 2367861Sgblack@eecs.umich.eduif options.timesync: 2377861Sgblack@eecs.umich.edu root.time_sync_enable = True 2387861Sgblack@eecs.umich.edu 2398635Schris.emmons@arm.comif options.frame_capture: 2408635Schris.emmons@arm.com VncServer.frame_capture = True 2418635Schris.emmons@arm.com 2429061Snilay@cs.wisc.eduSimulation.setWorkCountOptions(test_sys, options) 2433481Shsul@eecs.umich.eduSimulation.run(options, root, test_sys, FutureClass) 244