fs.py revision 9793 
1# Copyright (c) 2010-2013 ARM Limited
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13# Copyright (c) 2006-2007 The Regents of The University of Michigan
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39# Authors: Ali Saidi
40
41import optparse
42import sys
43
44import m5
45from m5.defines import buildEnv
46from m5.objects import *
47from m5.util import addToPath, fatal
48
49addToPath('../common')
50
51from FSConfig import *
52from SysPaths import *
53from Benchmarks import *
54import Simulation
55import CacheConfig
56from Caches import *
57import Options
58
59parser = optparse.OptionParser()
60Options.addCommonOptions(parser)
61Options.addFSOptions(parser)
62
63(options, args) = parser.parse_args()
64
65if args:
66    print "Error: script doesn't take any positional arguments"
67    sys.exit(1)
68
69# driver system CPU is always simple... note this is an assignment of
70# a class, not an instance.
71DriveCPUClass = AtomicSimpleCPU
72drive_mem_mode = 'atomic'
73
74# Check if KVM support has been enabled, we might need to do VM
75# configuration if that's the case.
76have_kvm_support = 'BaseKvmCPU' in globals()
77def is_kvm_cpu(cpu_class):
78    return have_kvm_support and cpu_class != None and \
79        issubclass(cpu_class, BaseKvmCPU)
80
81# system under test can be any CPU
82(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
83
84# Match the memories with the CPUs, the driver system always simple,
85# and based on the options for the test system
86DriveMemClass = SimpleMemory
87TestMemClass = Simulation.setMemClass(options)
88
89if options.benchmark:
90    try:
91        bm = Benchmarks[options.benchmark]
92    except KeyError:
93        print "Error benchmark %s has not been defined." % options.benchmark
94        print "Valid benchmarks are: %s" % DefinedBenchmarks
95        sys.exit(1)
96else:
97    if options.dual:
98        bm = [SysConfig(disk=options.disk_image, mem=options.mem_size), SysConfig(disk=options.disk_image, mem=options.mem_size)]
99    else:
100        bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)]
101
102np = options.num_cpus
103
104if buildEnv['TARGET_ISA'] == "alpha":
105    test_sys = makeLinuxAlphaSystem(test_mem_mode, TestMemClass, bm[0])
106elif buildEnv['TARGET_ISA'] == "mips":
107    test_sys = makeLinuxMipsSystem(test_mem_mode, TestMemClass, bm[0])
108elif buildEnv['TARGET_ISA'] == "sparc":
109    test_sys = makeSparcSystem(test_mem_mode, TestMemClass, bm[0])
110elif buildEnv['TARGET_ISA'] == "x86":
111    test_sys = makeLinuxX86System(test_mem_mode, TestMemClass,
112                                  options.num_cpus, bm[0])
113elif buildEnv['TARGET_ISA'] == "arm":
114    test_sys = makeArmSystem(test_mem_mode, options.machine_type,
115                             TestMemClass, bm[0], options.dtb_filename,
116                             bare_metal=options.bare_metal)
117else:
118    fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
119
120# Create a source clock for the system and set the clock period
121test_sys.clk_domain = SrcClockDomain(clock =  options.sys_clock)
122
123# Create a source clock for the CPUs and set the clock period
124test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock)
125
126if options.kernel is not None:
127    test_sys.kernel = binary(options.kernel)
128
129if options.script is not None:
130    test_sys.readfile = options.script
131
132test_sys.init_param = options.init_param
133
134# For now, assign all the CPUs to the same clock domain
135test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
136                for i in xrange(np)]
137
138if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
139    test_sys.vm = KvmVM()
140
141if options.caches or options.l2cache:
142    # By default the IOCache runs at the system clock
143    test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
144    test_sys.iocache.cpu_side = test_sys.iobus.master
145    test_sys.iocache.mem_side = test_sys.membus.slave
146else:
147    test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
148    test_sys.iobridge.slave = test_sys.iobus.master
149    test_sys.iobridge.master = test_sys.membus.slave
150
151# Sanity check
152if options.fastmem:
153    if TestCPUClass != AtomicSimpleCPU:
154        fatal("Fastmem can only be used with atomic CPU!")
155    if (options.caches or options.l2cache):
156        fatal("You cannot use fastmem in combination with caches!")
157
158for i in xrange(np):
159    if options.fastmem:
160        test_sys.cpu[i].fastmem = True
161    if options.checker:
162        test_sys.cpu[i].addCheckerCpu()
163    test_sys.cpu[i].createThreads()
164
165CacheConfig.config_cache(options, test_sys)
166
167if len(bm) == 2:
168    if buildEnv['TARGET_ISA'] == 'alpha':
169        drive_sys = makeLinuxAlphaSystem(drive_mem_mode, DriveMemClass, bm[1])
170    elif buildEnv['TARGET_ISA'] == 'mips':
171        drive_sys = makeLinuxMipsSystem(drive_mem_mode, DriveMemClass, bm[1])
172    elif buildEnv['TARGET_ISA'] == 'sparc':
173        drive_sys = makeSparcSystem(drive_mem_mode, DriveMemClass, bm[1])
174    elif buildEnv['TARGET_ISA'] == 'x86':
175        drive_sys = makeX86System(drive_mem_mode, DriveMemClass, np, bm[1])
176    elif buildEnv['TARGET_ISA'] == 'arm':
177        drive_sys = makeArmSystem(drive_mem_mode, options.machine_type,
178                                  DriveMemClass, bm[1])
179
180    # Create a source clock for the system and set the clock period
181    drive_sys.clk_domain = SrcClockDomain(clock =  options.sys_clock)
182
183    # Create a source clock for the CPUs and set the clock period
184    drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock)
185
186    drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain,
187                                  cpu_id=0)
188    drive_sys.cpu.createThreads()
189    drive_sys.cpu.createInterruptController()
190    drive_sys.cpu.connectAllPorts(drive_sys.membus)
191    if options.fastmem:
192        drive_sys.cpu.fastmem = True
193    if options.kernel is not None:
194        drive_sys.kernel = binary(options.kernel)
195
196    if is_kvm_cpu(DriveCPUClass):
197        drive_sys.vm = KvmVM()
198
199    drive_sys.iobridge = Bridge(delay='50ns',
200                                ranges = drive_sys.mem_ranges)
201    drive_sys.iobridge.slave = drive_sys.iobus.master
202    drive_sys.iobridge.master = drive_sys.membus.slave
203
204    drive_sys.init_param = options.init_param
205    root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
206elif len(bm) == 1:
207    root = Root(full_system=True, system=test_sys)
208else:
209    print "Error I don't know how to create more than 2 systems."
210    sys.exit(1)
211
212if options.timesync:
213    root.time_sync_enable = True
214
215if options.frame_capture:
216    VncServer.frame_capture = True
217
218Simulation.setWorkCountOptions(test_sys, options)
219Simulation.run(options, root, test_sys, FutureClass)
220