fs.py revision 8659
12292SN/A# Copyright (c) 2010 ARM Limited 22292SN/A# All rights reserved. 32292SN/A# 42292SN/A# The license below extends only to copyright in the software and shall 52292SN/A# not be construed as granting a license to any other intellectual 62292SN/A# property including but not limited to intellectual property relating 72292SN/A# to a hardware implementation of the functionality of the software 82292SN/A# licensed hereunder. You may use the software subject to the license 92292SN/A# terms below provided that you ensure that this notice is replicated 102292SN/A# unmodified and in its entirety in all distributions of the software, 112292SN/A# modified or unmodified, in source code or in binary form. 122292SN/A# 132292SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 142292SN/A# All rights reserved. 152292SN/A# 162292SN/A# Redistribution and use in source and binary forms, with or without 172292SN/A# modification, are permitted provided that the following conditions are 182292SN/A# met: redistributions of source code must retain the above copyright 192292SN/A# notice, this list of conditions and the following disclaimer; 202292SN/A# redistributions in binary form must reproduce the above copyright 212292SN/A# notice, this list of conditions and the following disclaimer in the 222292SN/A# documentation and/or other materials provided with the distribution; 232292SN/A# neither the name of the copyright holders nor the names of its 242292SN/A# contributors may be used to endorse or promote products derived from 252292SN/A# this software without specific prior written permission. 262292SN/A# 272689Sktlim@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 282689Sktlim@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 292689Sktlim@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 302292SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 312292SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 323326Sktlim@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 332733Sktlim@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 342733Sktlim@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 352907Sktlim@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 362292SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 372292SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 382722Sktlim@umich.edu# 392669Sktlim@umich.edu# Authors: Ali Saidi 402292SN/A 412790Sktlim@umich.eduimport optparse 422790Sktlim@umich.eduimport os 432790Sktlim@umich.eduimport sys 442790Sktlim@umich.edu 452669Sktlim@umich.eduimport m5 462678Sktlim@umich.edufrom m5.defines import buildEnv 472678Sktlim@umich.edufrom m5.objects import * 482678Sktlim@umich.edufrom m5.util import addToPath, fatal 492292SN/A 502678Sktlim@umich.eduif not buildEnv['FULL_SYSTEM']: 512292SN/A fatal("This script requires full-system mode (*_FS).") 522292SN/A 532669Sktlim@umich.eduaddToPath('../common') 542292SN/A 552678Sktlim@umich.edufrom FSConfig import * 562292SN/Afrom SysPaths import * 572678Sktlim@umich.edufrom Benchmarks import * 582678Sktlim@umich.eduimport Simulation 592678Sktlim@umich.eduimport CacheConfig 604319Sktlim@umich.edufrom Caches import * 614319Sktlim@umich.edu 624319Sktlim@umich.edu# Get paths we might need. It's expected this file is in m5/configs/example. 634319Sktlim@umich.educonfig_path = os.path.dirname(os.path.abspath(__file__)) 644319Sktlim@umich.educonfig_root = os.path.dirname(config_path) 652678Sktlim@umich.edu 662678Sktlim@umich.eduparser = optparse.OptionParser() 672292SN/A 682678Sktlim@umich.edu# Simulation options 692678Sktlim@umich.eduparser.add_option("--timesync", action="store_true", 702678Sktlim@umich.edu help="Prevent simulated time from getting ahead of real time") 712678Sktlim@umich.edu 722678Sktlim@umich.edu# System options 732678Sktlim@umich.eduparser.add_option("--kernel", action="store", type="string") 742292SN/Aparser.add_option("--script", action="store", type="string") 752678Sktlim@umich.eduparser.add_option("--frame-capture", action="store_true", 762678Sktlim@umich.edu help="Stores changed frame buffers from the VNC server to compressed "\ 772678Sktlim@umich.edu "files in the gem5 output directory") 782678Sktlim@umich.edu 792678Sktlim@umich.eduif buildEnv['TARGET_ISA'] == "arm": 802678Sktlim@umich.edu parser.add_option("--bare-metal", action="store_true", 812678Sktlim@umich.edu help="Provide the raw system without the linux specific bits") 822698Sktlim@umich.edu parser.add_option("--machine-type", action="store", type="choice", 832344SN/A choices=ArmMachineType.map.keys(), default="RealView_PBX") 842678Sktlim@umich.edu# Benchmark options 852678Sktlim@umich.eduparser.add_option("--dual", action="store_true", 862678Sktlim@umich.edu help="Simulate two systems attached with an ethernet link") 872820Sktlim@umich.eduparser.add_option("-b", "--benchmark", action="store", type="string", 882678Sktlim@umich.edu dest="benchmark", 892678Sktlim@umich.edu help="Specify the benchmark to run. Available benchmarks: %s"\ 902678Sktlim@umich.edu % DefinedBenchmarks) 912678Sktlim@umich.edu 922678Sktlim@umich.edu# Metafile options 932678Sktlim@umich.eduparser.add_option("--etherdump", action="store", type="string", dest="etherdump", 942678Sktlim@umich.edu help="Specify the filename to dump a pcap capture of the" \ 952678Sktlim@umich.edu "ethernet traffic") 962344SN/A 972307SN/Aexecfile(os.path.join(config_root, "common", "Options.py")) 982678Sktlim@umich.edu 994032Sktlim@umich.edu(options, args) = parser.parse_args() 1002678Sktlim@umich.edu 1012292SN/Aif args: 1022292SN/A print "Error: script doesn't take any positional arguments" 1032292SN/A sys.exit(1) 1042292SN/A 1052678Sktlim@umich.edu# driver system CPU is always simple... note this is an assignment of 1062678Sktlim@umich.edu# a class, not an instance. 1072292SN/ADriveCPUClass = AtomicSimpleCPU 1082292SN/Adrive_mem_mode = 'atomic' 1092292SN/A 1102292SN/A# system under test can be any CPU 1112292SN/A(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 1122292SN/A 1134329Sktlim@umich.eduTestCPUClass.clock = '2GHz' 1144329Sktlim@umich.eduDriveCPUClass.clock = '2GHz' 1152292SN/A 1164329Sktlim@umich.eduif options.benchmark: 1174329Sktlim@umich.edu try: 1184329Sktlim@umich.edu bm = Benchmarks[options.benchmark] 1194329Sktlim@umich.edu except KeyError: 1202292SN/A print "Error benchmark %s has not been defined." % options.benchmark 1212307SN/A print "Valid benchmarks are: %s" % DefinedBenchmarks 1222307SN/A sys.exit(1) 1232907Sktlim@umich.eduelse: 1242907Sktlim@umich.edu if options.dual: 1252292SN/A bm = [SysConfig(), SysConfig()] 1262292SN/A else: 1272329SN/A bm = [SysConfig()] 1282329SN/A 1292329SN/Anp = options.num_cpus 1302292SN/A 1312292SN/Aif buildEnv['TARGET_ISA'] == "alpha": 1322292SN/A test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0]) 1332292SN/Aelif buildEnv['TARGET_ISA'] == "mips": 1342292SN/A test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0]) 1352292SN/Aelif buildEnv['TARGET_ISA'] == "sparc": 1362292SN/A test_sys = makeSparcSystem(test_mem_mode, bm[0]) 1372292SN/Aelif buildEnv['TARGET_ISA'] == "x86": 1382292SN/A test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0]) 1392292SN/A setWorkCountOptions(test_sys, options) 1402292SN/Aelif buildEnv['TARGET_ISA'] == "arm": 1413492Sktlim@umich.edu test_sys = makeArmSystem(test_mem_mode, 1422329SN/A options.machine_type, bm[0], 1432292SN/A bare_metal=options.bare_metal) 1442292SN/A setWorkCountOptions(test_sys, options) 1452292SN/Aelse: 1462292SN/A fatal("incapable of building non-alpha or non-sparc full system!") 1472292SN/A 1482292SN/Aif options.kernel is not None: 1492292SN/A test_sys.kernel = binary(options.kernel) 1502292SN/A 1512292SN/Aif options.script is not None: 1522292SN/A test_sys.readfile = options.script 1532292SN/A 1542292SN/Atest_sys.init_param = options.init_param 1552292SN/A 1562292SN/Atest_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)] 1572292SN/A 1582292SN/ACacheConfig.config_cache(options, test_sys) 1592292SN/A 1602727Sktlim@umich.eduif options.caches or options.l2cache: 1612727Sktlim@umich.edu if bm[0]: 1622727Sktlim@umich.edu mem_size = bm[0].mem() 1632727Sktlim@umich.edu else: 1642727Sktlim@umich.edu mem_size = SysConfig().mem() 1652727Sktlim@umich.edu # For x86, we need to poke a hole for interrupt messages to get back to the 1662727Sktlim@umich.edu # CPU. These use a portion of the physical address space which has a 1672727Sktlim@umich.edu # non-zero prefix in the top nibble. Normal memory accesses have a 0 1682727Sktlim@umich.edu # prefix. 1692727Sktlim@umich.edu if buildEnv['TARGET_ISA'] == 'x86': 1702727Sktlim@umich.edu test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max >> 4)] 1712727Sktlim@umich.edu else: 1722727Sktlim@umich.edu test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max)] 1732727Sktlim@umich.edu test_sys.bridge.filter_ranges_b=[AddrRange(mem_size)] 1742727Sktlim@umich.edu test_sys.iocache = IOCache(addr_range=mem_size) 1752727Sktlim@umich.edu test_sys.iocache.cpu_side = test_sys.iobus.port 1762727Sktlim@umich.edu test_sys.iocache.mem_side = test_sys.membus.port 1772727Sktlim@umich.edu 1782361SN/Afor i in xrange(np): 1792361SN/A if options.fastmem: 1802361SN/A test_sys.cpu[i].physmem_port = test_sys.physmem.port 1812361SN/A 1822727Sktlim@umich.eduif buildEnv['TARGET_ISA'] == 'mips': 1832727Sktlim@umich.edu setMipsOptions(TestCPUClass) 1842727Sktlim@umich.edu 1852727Sktlim@umich.eduif len(bm) == 2: 1862727Sktlim@umich.edu if buildEnv['TARGET_ISA'] == 'alpha': 1872727Sktlim@umich.edu drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1]) 1882727Sktlim@umich.edu elif buildEnv['TARGET_ISA'] == 'mips': 1892727Sktlim@umich.edu drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1]) 1902727Sktlim@umich.edu elif buildEnv['TARGET_ISA'] == 'sparc': 1912727Sktlim@umich.edu drive_sys = makeSparcSystem(drive_mem_mode, bm[1]) 1922727Sktlim@umich.edu elif buildEnv['TARGET_ISA'] == 'x86': 1932727Sktlim@umich.edu drive_sys = makeX86System(drive_mem_mode, np, bm[1]) 1942727Sktlim@umich.edu elif buildEnv['TARGET_ISA'] == 'arm': 1952727Sktlim@umich.edu drive_sys = makeArmSystem(drive_mem_mode, 1962727Sktlim@umich.edu machine_options.machine_type, bm[1]) 1972727Sktlim@umich.edu drive_sys.cpu = DriveCPUClass(cpu_id=0) 1982727Sktlim@umich.edu drive_sys.cpu.connectAllPorts(drive_sys.membus) 1992727Sktlim@umich.edu if options.fastmem: 2002727Sktlim@umich.edu drive_sys.cpu.physmem_port = drive_sys.physmem.port 2012727Sktlim@umich.edu if options.kernel is not None: 2022727Sktlim@umich.edu drive_sys.kernel = binary(options.kernel) 2032727Sktlim@umich.edu 2042727Sktlim@umich.edu drive_sys.init_param = options.init_param 2054329Sktlim@umich.edu root = makeDualRoot(test_sys, drive_sys, options.etherdump) 2064329Sktlim@umich.eduelif len(bm) == 1: 2074329Sktlim@umich.edu root = Root(system=test_sys) 2084329Sktlim@umich.eduelse: 2094329Sktlim@umich.edu print "Error I don't know how to create more than 2 systems." 2104329Sktlim@umich.edu sys.exit(1) 2114329Sktlim@umich.edu 2124329Sktlim@umich.eduif options.timesync: 2134329Sktlim@umich.edu root.time_sync_enable = True 2144329Sktlim@umich.edu 2154329Sktlim@umich.eduif options.frame_capture: 2164329Sktlim@umich.edu VncServer.frame_capture = True 2174329Sktlim@umich.edu 2182292SN/ASimulation.run(options, root, test_sys, FutureClass) 2192292SN/A