fs.py revision 13803
16657Snate@binkert.org# Copyright (c) 2010-2013, 2016, 2019 ARM Limited 26657Snate@binkert.org# All rights reserved. 36657Snate@binkert.org# 46657Snate@binkert.org# The license below extends only to copyright in the software and shall 56657Snate@binkert.org# not be construed as granting a license to any other intellectual 66657Snate@binkert.org# property including but not limited to intellectual property relating 76657Snate@binkert.org# to a hardware implementation of the functionality of the software 86657Snate@binkert.org# licensed hereunder. You may use the software subject to the license 96657Snate@binkert.org# terms below provided that you ensure that this notice is replicated 106657Snate@binkert.org# unmodified and in its entirety in all distributions of the software, 116657Snate@binkert.org# modified or unmodified, in source code or in binary form. 126657Snate@binkert.org# 136657Snate@binkert.org# Copyright (c) 2012-2014 Mark D. Hill and David A. Wood 146657Snate@binkert.org# Copyright (c) 2009-2011 Advanced Micro Devices, Inc. 156657Snate@binkert.org# Copyright (c) 2006-2007 The Regents of The University of Michigan 166657Snate@binkert.org# All rights reserved. 176657Snate@binkert.org# 186657Snate@binkert.org# Redistribution and use in source and binary forms, with or without 196657Snate@binkert.org# modification, are permitted provided that the following conditions are 206657Snate@binkert.org# met: redistributions of source code must retain the above copyright 216657Snate@binkert.org# notice, this list of conditions and the following disclaimer; 226657Snate@binkert.org# redistributions in binary form must reproduce the above copyright 236657Snate@binkert.org# notice, this list of conditions and the following disclaimer in the 246657Snate@binkert.org# documentation and/or other materials provided with the distribution; 256657Snate@binkert.org# neither the name of the copyright holders nor the names of its 266657Snate@binkert.org# contributors may be used to endorse or promote products derived from 276657Snate@binkert.org# this software without specific prior written permission. 286999Snate@binkert.org# 296657Snate@binkert.org# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306657Snate@binkert.org# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316657Snate@binkert.org# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326657Snate@binkert.org# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336657Snate@binkert.org# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346882SBrad.Beckmann@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 357055Snate@binkert.org# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366882SBrad.Beckmann@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376882SBrad.Beckmann@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386882SBrad.Beckmann@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396882SBrad.Beckmann@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406882SBrad.Beckmann@amd.com# 416888SBrad.Beckmann@amd.com# Authors: Ali Saidi 426882SBrad.Beckmann@amd.com# Brad Beckmann 436882SBrad.Beckmann@amd.com 446657Snate@binkert.orgfrom __future__ import print_function 456657Snate@binkert.orgfrom __future__ import absolute_import 466657Snate@binkert.org 476657Snate@binkert.orgimport optparse 486657Snate@binkert.orgimport sys 497839Snilay@cs.wisc.edu 506657Snate@binkert.orgimport m5 516882SBrad.Beckmann@amd.comfrom m5.defines import buildEnv 526882SBrad.Beckmann@amd.comfrom m5.objects import * 536882SBrad.Beckmann@amd.comfrom m5.util import addToPath, fatal, warn 546882SBrad.Beckmann@amd.comfrom m5.util.fdthelper import * 556882SBrad.Beckmann@amd.com 566882SBrad.Beckmann@amd.comaddToPath('../') 576657Snate@binkert.org 586657Snate@binkert.orgfrom ruby import Ruby 596657Snate@binkert.org 606657Snate@binkert.orgfrom common.FSConfig import * 616657Snate@binkert.orgfrom common.SysPaths import * 626657Snate@binkert.orgfrom common.Benchmarks import * 636657Snate@binkert.orgfrom common import Simulation 646657Snate@binkert.orgfrom common import CacheConfig 656657Snate@binkert.orgfrom common import MemConfig 667839Snilay@cs.wisc.edufrom common import CpuConfig 677839Snilay@cs.wisc.edufrom common import BPConfig 686657Snate@binkert.orgfrom common.Caches import * 696657Snate@binkert.orgfrom common import Options 706657Snate@binkert.org 716657Snate@binkert.orgdef cmd_line_template(): 726657Snate@binkert.org if options.command_line and options.command_line_file: 736657Snate@binkert.org print("Error: --command-line and --command-line-file are " 746657Snate@binkert.org "mutually exclusive") 756657Snate@binkert.org sys.exit(1) 766657Snate@binkert.org if options.command_line: 776657Snate@binkert.org return options.command_line 786657Snate@binkert.org if options.command_line_file: 796657Snate@binkert.org return open(options.command_line_file).read().strip() 806657Snate@binkert.org return None 816657Snate@binkert.org 826657Snate@binkert.orgdef build_test_system(np): 836657Snate@binkert.org cmdline = cmd_line_template() 846657Snate@binkert.org if buildEnv['TARGET_ISA'] == "alpha": 856657Snate@binkert.org test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby, 866657Snate@binkert.org cmdline=cmdline) 876657Snate@binkert.org elif buildEnv['TARGET_ISA'] == "mips": 886779SBrad.Beckmann@amd.com test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline) 896657Snate@binkert.org elif buildEnv['TARGET_ISA'] == "sparc": 906657Snate@binkert.org test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline) 916657Snate@binkert.org elif buildEnv['TARGET_ISA'] == "x86": 926657Snate@binkert.org test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0], 936657Snate@binkert.org options.ruby, cmdline=cmdline) 946657Snate@binkert.org elif buildEnv['TARGET_ISA'] == "arm": 956657Snate@binkert.org test_sys = makeArmSystem(test_mem_mode, options.machine_type, 966657Snate@binkert.org options.num_cpus, bm[0], options.dtb_filename, 976657Snate@binkert.org bare_metal=options.bare_metal, 986657Snate@binkert.org cmdline=cmdline, 996657Snate@binkert.org external_memory= 1006657Snate@binkert.org options.external_memory_system, 1016657Snate@binkert.org ruby=options.ruby, 1026657Snate@binkert.org security=options.enable_security_extensions) 1036657Snate@binkert.org if options.enable_context_switch_stats_dump: 1046657Snate@binkert.org test_sys.enable_context_switch_stats_dump = True 1056657Snate@binkert.org else: 1066657Snate@binkert.org fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) 1076657Snate@binkert.org 1086657Snate@binkert.org # Set the cache line size for the entire system 1096657Snate@binkert.org test_sys.cache_line_size = options.cacheline_size 1106657Snate@binkert.org 1116657Snate@binkert.org # Create a top-level voltage domain 1126657Snate@binkert.org test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 1137839Snilay@cs.wisc.edu 1147839Snilay@cs.wisc.edu # Create a source clock for the system and set the clock period 1157839Snilay@cs.wisc.edu test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, 1167839Snilay@cs.wisc.edu voltage_domain = test_sys.voltage_domain) 1177839Snilay@cs.wisc.edu 1187839Snilay@cs.wisc.edu # Create a CPU voltage domain 1197839Snilay@cs.wisc.edu test_sys.cpu_voltage_domain = VoltageDomain() 1207839Snilay@cs.wisc.edu 1217839Snilay@cs.wisc.edu # Create a source clock for the CPUs and set the clock period 1227839Snilay@cs.wisc.edu test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 1237839Snilay@cs.wisc.edu voltage_domain = 1247839Snilay@cs.wisc.edu test_sys.cpu_voltage_domain) 1257839Snilay@cs.wisc.edu 1267839Snilay@cs.wisc.edu if options.kernel is not None: 1277839Snilay@cs.wisc.edu test_sys.kernel = binary(options.kernel) 1286657Snate@binkert.org else: 1296657Snate@binkert.org print("Error: a kernel must be provided to run in full system mode") 1306657Snate@binkert.org sys.exit(1) 1316657Snate@binkert.org 1326657Snate@binkert.org if options.script is not None: 1336657Snate@binkert.org test_sys.readfile = options.script 1346657Snate@binkert.org 1356657Snate@binkert.org if options.lpae: 1366657Snate@binkert.org test_sys.have_lpae = True 1376657Snate@binkert.org 1386657Snate@binkert.org if options.virtualisation: 1396657Snate@binkert.org test_sys.have_virtualization = True 1406657Snate@binkert.org 1416657Snate@binkert.org test_sys.init_param = options.init_param 1426657Snate@binkert.org 1436657Snate@binkert.org # For now, assign all the CPUs to the same clock domain 1446657Snate@binkert.org test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) 1456657Snate@binkert.org for i in range(np)] 1466657Snate@binkert.org 1476657Snate@binkert.org if CpuConfig.is_kvm_cpu(TestCPUClass) or CpuConfig.is_kvm_cpu(FutureClass): 1486657Snate@binkert.org test_sys.kvm_vm = KvmVM() 1496657Snate@binkert.org 1506657Snate@binkert.org if options.ruby: 1516657Snate@binkert.org bootmem = getattr(test_sys, 'bootmem', None) 1526657Snate@binkert.org Ruby.create_system(options, True, test_sys, test_sys.iobus, 1536657Snate@binkert.org test_sys._dma_ports, bootmem) 1546657Snate@binkert.org 1556657Snate@binkert.org # Create a seperate clock domain for Ruby 1566657Snate@binkert.org test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 1576657Snate@binkert.org voltage_domain = test_sys.voltage_domain) 1586657Snate@binkert.org 1596877Ssteve.reinhardt@amd.com # Connect the ruby io port to the PIO bus, 1606657Snate@binkert.org # assuming that there is just one such port. 1616657Snate@binkert.org test_sys.iobus.master = test_sys.ruby._io_port.slave 1626657Snate@binkert.org 1636657Snate@binkert.org for (i, cpu) in enumerate(test_sys.cpu): 1646657Snate@binkert.org # 1656657Snate@binkert.org # Tie the cpu ports to the correct ruby system ports 1667542SBrad.Beckmann@amd.com # 1677542SBrad.Beckmann@amd.com cpu.clk_domain = test_sys.cpu_clk_domain 1686657Snate@binkert.org cpu.createThreads() 1696657Snate@binkert.org cpu.createInterruptController() 1706657Snate@binkert.org 1716657Snate@binkert.org cpu.icache_port = test_sys.ruby._cpu_ports[i].slave 1726877Ssteve.reinhardt@amd.com cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave 1736999Snate@binkert.org 1746877Ssteve.reinhardt@amd.com if buildEnv['TARGET_ISA'] in ("x86", "arm"): 1756877Ssteve.reinhardt@amd.com cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave 1766877Ssteve.reinhardt@amd.com cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave 1776877Ssteve.reinhardt@amd.com 1786877Ssteve.reinhardt@amd.com if buildEnv['TARGET_ISA'] in "x86": 1796877Ssteve.reinhardt@amd.com cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master 1806877Ssteve.reinhardt@amd.com cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave 1816877Ssteve.reinhardt@amd.com cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master 1826877Ssteve.reinhardt@amd.com 1836877Ssteve.reinhardt@amd.com else: 1846877Ssteve.reinhardt@amd.com if options.caches or options.l2cache: 1856877Ssteve.reinhardt@amd.com # By default the IOCache runs at the system clock 1866877Ssteve.reinhardt@amd.com test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges) 1876877Ssteve.reinhardt@amd.com test_sys.iocache.cpu_side = test_sys.iobus.master 1886877Ssteve.reinhardt@amd.com test_sys.iocache.mem_side = test_sys.membus.slave 1896877Ssteve.reinhardt@amd.com elif not options.external_memory_system: 1906882SBrad.Beckmann@amd.com test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) 1916882SBrad.Beckmann@amd.com test_sys.iobridge.slave = test_sys.iobus.master 1926882SBrad.Beckmann@amd.com test_sys.iobridge.master = test_sys.membus.slave 1936882SBrad.Beckmann@amd.com 1946882SBrad.Beckmann@amd.com # Sanity check 1956882SBrad.Beckmann@amd.com if options.simpoint_profile: 1966882SBrad.Beckmann@amd.com if not CpuConfig.is_noncaching_cpu(TestCPUClass): 1976877Ssteve.reinhardt@amd.com fatal("SimPoint generation should be done with atomic cpu") 1986877Ssteve.reinhardt@amd.com if np > 1: 1996877Ssteve.reinhardt@amd.com fatal("SimPoint generation not supported with more than one CPUs") 2006877Ssteve.reinhardt@amd.com 2016657Snate@binkert.org for i in range(np): 2026657Snate@binkert.org if options.simpoint_profile: 2036999Snate@binkert.org test_sys.cpu[i].addSimPointProbe(options.simpoint_interval) 2046657Snate@binkert.org if options.checker: 2056657Snate@binkert.org test_sys.cpu[i].addCheckerCpu() 2066657Snate@binkert.org if options.bp_type: 2076657Snate@binkert.org bpClass = BPConfig.get(options.bp_type) 2086657Snate@binkert.org test_sys.cpu[i].branchPred = bpClass() 2096657Snate@binkert.org test_sys.cpu[i].createThreads() 2107007Snate@binkert.org 2116657Snate@binkert.org # If elastic tracing is enabled when not restoring from checkpoint and 2126657Snate@binkert.org # when not fast forwarding using the atomic cpu, then check that the 2136657Snate@binkert.org # TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check 2146657Snate@binkert.org # passes then attach the elastic trace probe. 2156657Snate@binkert.org # If restoring from checkpoint or fast forwarding, the code that does this for 2167007Snate@binkert.org # FutureCPUClass is in the Simulation module. If the check passes then the 2177007Snate@binkert.org # elastic trace probe is attached to the switch CPUs. 2186657Snate@binkert.org if options.elastic_trace_en and options.checkpoint_restore == None and \ 2197002Snate@binkert.org not options.fast_forward: 2207002Snate@binkert.org CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options) 2217002Snate@binkert.org 2227002Snate@binkert.org CacheConfig.config_cache(options, test_sys) 2236877Ssteve.reinhardt@amd.com 2246877Ssteve.reinhardt@amd.com MemConfig.config_mem(options, test_sys) 2256657Snate@binkert.org 2266657Snate@binkert.org return test_sys 2276657Snate@binkert.org 2286657Snate@binkert.orgdef build_drive_system(np): 2296657Snate@binkert.org # driver system CPU is always simple, so is the memory 2306657Snate@binkert.org # Note this is an assignment of a class, not an instance. 2317542SBrad.Beckmann@amd.com DriveCPUClass = AtomicSimpleCPU 2326657Snate@binkert.org drive_mem_mode = 'atomic' 2336657Snate@binkert.org DriveMemClass = SimpleMemory 2346657Snate@binkert.org 2356657Snate@binkert.org cmdline = cmd_line_template() 2366793SBrad.Beckmann@amd.com if buildEnv['TARGET_ISA'] == 'alpha': 2376657Snate@binkert.org drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1], 2386657Snate@binkert.org cmdline=cmdline) 2396657Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'mips': 2406657Snate@binkert.org drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1], cmdline=cmdline) 2416657Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'sparc': 2427002Snate@binkert.org drive_sys = makeSparcSystem(drive_mem_mode, bm[1], cmdline=cmdline) 2436657Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'x86': 2447007Snate@binkert.org drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1], 2457007Snate@binkert.org cmdline=cmdline) 2467007Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'arm': 2477007Snate@binkert.org drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, np, 2487007Snate@binkert.org bm[1], options.dtb_filename, cmdline=cmdline) 2496657Snate@binkert.org 2506877Ssteve.reinhardt@amd.com # Create a top-level voltage domain 2516877Ssteve.reinhardt@amd.com drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 2526657Snate@binkert.org 2536877Ssteve.reinhardt@amd.com # Create a source clock for the system and set the clock period 2546657Snate@binkert.org drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, 2556657Snate@binkert.org voltage_domain = drive_sys.voltage_domain) 2567002Snate@binkert.org 2577002Snate@binkert.org # Create a CPU voltage domain 2586657Snate@binkert.org drive_sys.cpu_voltage_domain = VoltageDomain() 2597567SBrad.Beckmann@amd.com 2607567SBrad.Beckmann@amd.com # Create a source clock for the CPUs and set the clock period 2617922SBrad.Beckmann@amd.com drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 2626881SBrad.Beckmann@amd.com voltage_domain = 2637002Snate@binkert.org drive_sys.cpu_voltage_domain) 2647002Snate@binkert.org 2656657Snate@binkert.org drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain, 2667002Snate@binkert.org cpu_id=0) 2676902SBrad.Beckmann@amd.com drive_sys.cpu.createThreads() 2686863Sdrh5@cs.wisc.edu drive_sys.cpu.createInterruptController() 2696863Sdrh5@cs.wisc.edu drive_sys.cpu.connectAllPorts(drive_sys.membus) 2707007Snate@binkert.org if options.kernel is not None: 2716657Snate@binkert.org drive_sys.kernel = binary(options.kernel) 2726657Snate@binkert.org else: 2736657Snate@binkert.org print("Error: a kernel must be provided to run in full system mode") 2746657Snate@binkert.org sys.exit(1) 2756657Snate@binkert.org 2766657Snate@binkert.org if CpuConfig.is_kvm_cpu(DriveCPUClass): 2776882SBrad.Beckmann@amd.com drive_sys.kvm_vm = KvmVM() 2786882SBrad.Beckmann@amd.com 2796882SBrad.Beckmann@amd.com drive_sys.iobridge = Bridge(delay='50ns', 2806882SBrad.Beckmann@amd.com ranges = drive_sys.mem_ranges) 2816657Snate@binkert.org drive_sys.iobridge.slave = drive_sys.iobus.master 2826657Snate@binkert.org drive_sys.iobridge.master = drive_sys.membus.slave 2836657Snate@binkert.org 2846657Snate@binkert.org # Create the appropriate memory controllers and connect them to the 2857007Snate@binkert.org # memory bus 2867839Snilay@cs.wisc.edu drive_sys.mem_ctrls = [DriveMemClass(range = r) 2877839Snilay@cs.wisc.edu for r in drive_sys.mem_ranges] 2887839Snilay@cs.wisc.edu for i in range(len(drive_sys.mem_ctrls)): 2897839Snilay@cs.wisc.edu drive_sys.mem_ctrls[i].port = drive_sys.membus.master 2907839Snilay@cs.wisc.edu 2917839Snilay@cs.wisc.edu drive_sys.init_param = options.init_param 2927839Snilay@cs.wisc.edu 2937839Snilay@cs.wisc.edu return drive_sys 2947839Snilay@cs.wisc.edu 2957839Snilay@cs.wisc.edu# Add options 2967839Snilay@cs.wisc.eduparser = optparse.OptionParser() 2977839Snilay@cs.wisc.eduOptions.addCommonOptions(parser) 2987007Snate@binkert.orgOptions.addFSOptions(parser) 2997007Snate@binkert.org 3007007Snate@binkert.org# Add the ruby specific and protocol specific options 3017007Snate@binkert.orgif '--ruby' in sys.argv: 3027007Snate@binkert.org Ruby.define_options(parser) 3037839Snilay@cs.wisc.edu 3047839Snilay@cs.wisc.edu(options, args) = parser.parse_args() 3057839Snilay@cs.wisc.edu 3067839Snilay@cs.wisc.eduif args: 3077839Snilay@cs.wisc.edu print("Error: script doesn't take any positional arguments") 3087839Snilay@cs.wisc.edu sys.exit(1) 3097839Snilay@cs.wisc.edu 3107839Snilay@cs.wisc.edu# system under test can be any CPU 3117839Snilay@cs.wisc.edu(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 3127839Snilay@cs.wisc.edu 3137839Snilay@cs.wisc.edu# Match the memories with the CPUs, based on the options for the test system 3147839Snilay@cs.wisc.eduTestMemClass = Simulation.setMemClass(options) 3157007Snate@binkert.org 3167007Snate@binkert.orgif options.benchmark: 3177002Snate@binkert.org try: 3186657Snate@binkert.org bm = Benchmarks[options.benchmark] 3196657Snate@binkert.org except KeyError: 3206657Snate@binkert.org print("Error benchmark %s has not been defined." % options.benchmark) 3217055Snate@binkert.org print("Valid benchmarks are: %s" % DefinedBenchmarks) 3226657Snate@binkert.org sys.exit(1) 3236657Snate@binkert.orgelse: 3246657Snate@binkert.org if options.dual: 3256863Sdrh5@cs.wisc.edu bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device, 3267055Snate@binkert.org mem=options.mem_size, os_type=options.os_type), 3277567SBrad.Beckmann@amd.com SysConfig(disk=options.disk_image, rootdev=options.root_device, 3287567SBrad.Beckmann@amd.com mem=options.mem_size, os_type=options.os_type)] 3297567SBrad.Beckmann@amd.com else: 3307567SBrad.Beckmann@amd.com bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device, 3317567SBrad.Beckmann@amd.com mem=options.mem_size, os_type=options.os_type)] 3327542SBrad.Beckmann@amd.com 3337542SBrad.Beckmann@amd.comnp = options.num_cpus 3346657Snate@binkert.org 3357007Snate@binkert.orgtest_sys = build_test_system(np) 3366657Snate@binkert.orgif len(bm) == 2: 3376657Snate@binkert.org drive_sys = build_drive_system(np) 3386657Snate@binkert.org root = makeDualRoot(True, test_sys, drive_sys, options.etherdump) 3396657Snate@binkert.orgelif len(bm) == 1 and options.dist: 3406657Snate@binkert.org # This system is part of a dist-gem5 simulation 3416657Snate@binkert.org root = makeDistRoot(test_sys, 3426657Snate@binkert.org options.dist_rank, 3436657Snate@binkert.org options.dist_size, 3447839Snilay@cs.wisc.edu options.dist_server_name, 3457839Snilay@cs.wisc.edu options.dist_server_port, 3467839Snilay@cs.wisc.edu options.dist_sync_repeat, 3477839Snilay@cs.wisc.edu options.dist_sync_start, 3487839Snilay@cs.wisc.edu options.ethernet_linkspeed, 3497839Snilay@cs.wisc.edu options.ethernet_linkdelay, 3507839Snilay@cs.wisc.edu options.etherdump); 3517839Snilay@cs.wisc.eduelif len(bm) == 1: 3527839Snilay@cs.wisc.edu root = Root(full_system=True, system=test_sys) 3537839Snilay@cs.wisc.eduelse: 3547839Snilay@cs.wisc.edu print("Error I don't know how to create more than 2 systems.") 3557839Snilay@cs.wisc.edu sys.exit(1) 3567839Snilay@cs.wisc.edu 3577839Snilay@cs.wisc.eduif options.timesync: 3587839Snilay@cs.wisc.edu root.time_sync_enable = True 3597839Snilay@cs.wisc.edu 3606657Snate@binkert.orgif options.frame_capture: 3616657Snate@binkert.org VncServer.frame_capture = True 3626657Snate@binkert.org 3636657Snate@binkert.orgif buildEnv['TARGET_ISA'] == "arm" and not options.bare_metal \ 3647839Snilay@cs.wisc.edu and not options.dtb_filename: 3657839Snilay@cs.wisc.edu if options.machine_type not in ["VExpress_GEM5", "VExpress_GEM5_V1"]: 3667839Snilay@cs.wisc.edu warn("Can only correctly generate a dtb for VExpress_GEM5_V1 " \ 3677839Snilay@cs.wisc.edu "platforms, unless custom hardware models have been equipped "\ 3687839Snilay@cs.wisc.edu "with generation functionality.") 3697839Snilay@cs.wisc.edu 3707839Snilay@cs.wisc.edu # Generate a Device Tree 3717839Snilay@cs.wisc.edu for sysname in ('system', 'testsys', 'drivesys'): 3727839Snilay@cs.wisc.edu if hasattr(root, sysname): 3737839Snilay@cs.wisc.edu sys = getattr(root, sysname) 3747839Snilay@cs.wisc.edu sys.generateDtb(m5.options.outdir, '%s.dtb' % sysname) 3757839Snilay@cs.wisc.edu 3767839Snilay@cs.wisc.eduSimulation.setWorkCountOptions(test_sys, options) 3777839Snilay@cs.wisc.eduSimulation.run(options, root, test_sys, FutureClass) 3787839Snilay@cs.wisc.edu