fs.py revision 13684
113606Sciro.santilli@arm.com# Copyright (c) 2010-2013, 2016, 2019 ARM Limited 27586SAli.Saidi@arm.com# All rights reserved. 37586SAli.Saidi@arm.com# 47586SAli.Saidi@arm.com# The license below extends only to copyright in the software and shall 57586SAli.Saidi@arm.com# not be construed as granting a license to any other intellectual 67586SAli.Saidi@arm.com# property including but not limited to intellectual property relating 77586SAli.Saidi@arm.com# to a hardware implementation of the functionality of the software 87586SAli.Saidi@arm.com# licensed hereunder. You may use the software subject to the license 97586SAli.Saidi@arm.com# terms below provided that you ensure that this notice is replicated 107586SAli.Saidi@arm.com# unmodified and in its entirety in all distributions of the software, 117586SAli.Saidi@arm.com# modified or unmodified, in source code or in binary form. 127586SAli.Saidi@arm.com# 1310118Snilay@cs.wisc.edu# Copyright (c) 2012-2014 Mark D. Hill and David A. Wood 1410118Snilay@cs.wisc.edu# Copyright (c) 2009-2011 Advanced Micro Devices, Inc. 153970Sgblack@eecs.umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 163005Sstever@eecs.umich.edu# All rights reserved. 173005Sstever@eecs.umich.edu# 183005Sstever@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 193005Sstever@eecs.umich.edu# modification, are permitted provided that the following conditions are 203005Sstever@eecs.umich.edu# met: redistributions of source code must retain the above copyright 213005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 223005Sstever@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 233005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 243005Sstever@eecs.umich.edu# documentation and/or other materials provided with the distribution; 253005Sstever@eecs.umich.edu# neither the name of the copyright holders nor the names of its 263005Sstever@eecs.umich.edu# contributors may be used to endorse or promote products derived from 273005Sstever@eecs.umich.edu# this software without specific prior written permission. 283005Sstever@eecs.umich.edu# 293005Sstever@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 303005Sstever@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 313005Sstever@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 323005Sstever@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 333005Sstever@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 343005Sstever@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 353005Sstever@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 363005Sstever@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 373005Sstever@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 383005Sstever@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 393005Sstever@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 403005Sstever@eecs.umich.edu# 413005Sstever@eecs.umich.edu# Authors: Ali Saidi 4210118Snilay@cs.wisc.edu# Brad Beckmann 433005Sstever@eecs.umich.edu 4412564Sgabeblack@google.comfrom __future__ import print_function 4512564Sgabeblack@google.com 466654Snate@binkert.orgimport optparse 476654Snate@binkert.orgimport sys 482889SN/A 492710SN/Aimport m5 506654Snate@binkert.orgfrom m5.defines import buildEnv 516654Snate@binkert.orgfrom m5.objects import * 5212395Sswapnilster@gmail.comfrom m5.util import addToPath, fatal, warn 5312475Sglenn.bergmans@arm.comfrom m5.util.fdthelper import * 545457Ssaidi@eecs.umich.edu 5511670Sandreas.hansson@arm.comaddToPath('../') 5610118Snilay@cs.wisc.edu 5711670Sandreas.hansson@arm.comfrom ruby import Ruby 586654Snate@binkert.org 5911682Sandreas.hansson@arm.comfrom common.FSConfig import * 6011682Sandreas.hansson@arm.comfrom common.SysPaths import * 6111682Sandreas.hansson@arm.comfrom common.Benchmarks import * 6211682Sandreas.hansson@arm.comfrom common import Simulation 6311682Sandreas.hansson@arm.comfrom common import CacheConfig 6411682Sandreas.hansson@arm.comfrom common import MemConfig 6511790Sjungma@eit.uni-kl.defrom common import CpuConfig 6613432Spau.cabre@metempsy.comfrom common import BPConfig 6711682Sandreas.hansson@arm.comfrom common.Caches import * 6811682Sandreas.hansson@arm.comfrom common import Options 693444Sktlim@umich.edu 7010594Sgabeblack@google.comdef cmd_line_template(): 7110594Sgabeblack@google.com if options.command_line and options.command_line_file: 7212564Sgabeblack@google.com print("Error: --command-line and --command-line-file are " 7312564Sgabeblack@google.com "mutually exclusive") 7410594Sgabeblack@google.com sys.exit(1) 7510594Sgabeblack@google.com if options.command_line: 7610594Sgabeblack@google.com return options.command_line 7710594Sgabeblack@google.com if options.command_line_file: 7810594Sgabeblack@google.com return open(options.command_line_file).read().strip() 7910594Sgabeblack@google.com return None 8010594Sgabeblack@google.com 8110119Snilay@cs.wisc.edudef build_test_system(np): 8210594Sgabeblack@google.com cmdline = cmd_line_template() 8310119Snilay@cs.wisc.edu if buildEnv['TARGET_ISA'] == "alpha": 8410594Sgabeblack@google.com test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby, 8510594Sgabeblack@google.com cmdline=cmdline) 8610119Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == "mips": 8710594Sgabeblack@google.com test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline) 8810119Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == "sparc": 8910594Sgabeblack@google.com test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline) 9010119Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == "x86": 9110119Snilay@cs.wisc.edu test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0], 9210594Sgabeblack@google.com options.ruby, cmdline=cmdline) 9310119Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == "arm": 9410512SAli.Saidi@ARM.com test_sys = makeArmSystem(test_mem_mode, options.machine_type, 9510512SAli.Saidi@ARM.com options.num_cpus, bm[0], options.dtb_filename, 9610594Sgabeblack@google.com bare_metal=options.bare_metal, 9710780SCurtis.Dunham@arm.com cmdline=cmdline, 9812475Sglenn.bergmans@arm.com external_memory= 9912475Sglenn.bergmans@arm.com options.external_memory_system, 10012079Sgedare@rtems.org ruby=options.ruby, 10112079Sgedare@rtems.org security=options.enable_security_extensions) 10210119Snilay@cs.wisc.edu if options.enable_context_switch_stats_dump: 10310119Snilay@cs.wisc.edu test_sys.enable_context_switch_stats_dump = True 10410119Snilay@cs.wisc.edu else: 10510119Snilay@cs.wisc.edu fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) 1062566SN/A 10710119Snilay@cs.wisc.edu # Set the cache line size for the entire system 10810119Snilay@cs.wisc.edu test_sys.cache_line_size = options.cacheline_size 1099665Sandreas.hansson@arm.com 11010119Snilay@cs.wisc.edu # Create a top-level voltage domain 11110119Snilay@cs.wisc.edu test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 11210119Snilay@cs.wisc.edu 11310119Snilay@cs.wisc.edu # Create a source clock for the system and set the clock period 11410119Snilay@cs.wisc.edu test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, 11510119Snilay@cs.wisc.edu voltage_domain = test_sys.voltage_domain) 11610119Snilay@cs.wisc.edu 11710119Snilay@cs.wisc.edu # Create a CPU voltage domain 11810119Snilay@cs.wisc.edu test_sys.cpu_voltage_domain = VoltageDomain() 11910119Snilay@cs.wisc.edu 12010119Snilay@cs.wisc.edu # Create a source clock for the CPUs and set the clock period 12110119Snilay@cs.wisc.edu test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 12210119Snilay@cs.wisc.edu voltage_domain = 12310119Snilay@cs.wisc.edu test_sys.cpu_voltage_domain) 12410119Snilay@cs.wisc.edu 12510119Snilay@cs.wisc.edu if options.kernel is not None: 12610119Snilay@cs.wisc.edu test_sys.kernel = binary(options.kernel) 12710119Snilay@cs.wisc.edu 12810119Snilay@cs.wisc.edu if options.script is not None: 12910119Snilay@cs.wisc.edu test_sys.readfile = options.script 13010119Snilay@cs.wisc.edu 13110119Snilay@cs.wisc.edu if options.lpae: 13210119Snilay@cs.wisc.edu test_sys.have_lpae = True 13310119Snilay@cs.wisc.edu 13410119Snilay@cs.wisc.edu if options.virtualisation: 13510119Snilay@cs.wisc.edu test_sys.have_virtualization = True 13610119Snilay@cs.wisc.edu 13710119Snilay@cs.wisc.edu test_sys.init_param = options.init_param 13810119Snilay@cs.wisc.edu 13910119Snilay@cs.wisc.edu # For now, assign all the CPUs to the same clock domain 14010119Snilay@cs.wisc.edu test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) 14110119Snilay@cs.wisc.edu for i in xrange(np)] 14210119Snilay@cs.wisc.edu 14312941Sandreas.sandberg@arm.com if CpuConfig.is_kvm_cpu(TestCPUClass) or CpuConfig.is_kvm_cpu(FutureClass): 14411839SCurtis.Dunham@arm.com test_sys.kvm_vm = KvmVM() 14510119Snilay@cs.wisc.edu 14610119Snilay@cs.wisc.edu if options.ruby: 14712598Snikos.nikoleris@arm.com bootmem = getattr(test_sys, 'bootmem', None) 14810519Snilay@cs.wisc.edu Ruby.create_system(options, True, test_sys, test_sys.iobus, 14912598Snikos.nikoleris@arm.com test_sys._dma_ports, bootmem) 15010119Snilay@cs.wisc.edu 15110119Snilay@cs.wisc.edu # Create a seperate clock domain for Ruby 15210119Snilay@cs.wisc.edu test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 15310119Snilay@cs.wisc.edu voltage_domain = test_sys.voltage_domain) 15410119Snilay@cs.wisc.edu 15510547Snilay@cs.wisc.edu # Connect the ruby io port to the PIO bus, 15610547Snilay@cs.wisc.edu # assuming that there is just one such port. 15710547Snilay@cs.wisc.edu test_sys.iobus.master = test_sys.ruby._io_port.slave 15810547Snilay@cs.wisc.edu 15910119Snilay@cs.wisc.edu for (i, cpu) in enumerate(test_sys.cpu): 16010119Snilay@cs.wisc.edu # 16110119Snilay@cs.wisc.edu # Tie the cpu ports to the correct ruby system ports 16210119Snilay@cs.wisc.edu # 16310119Snilay@cs.wisc.edu cpu.clk_domain = test_sys.cpu_clk_domain 16410119Snilay@cs.wisc.edu cpu.createThreads() 16510119Snilay@cs.wisc.edu cpu.createInterruptController() 16610119Snilay@cs.wisc.edu 16710120Snilay@cs.wisc.edu cpu.icache_port = test_sys.ruby._cpu_ports[i].slave 16810120Snilay@cs.wisc.edu cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave 16910119Snilay@cs.wisc.edu 17011598Sandreas.sandberg@arm.com if buildEnv['TARGET_ISA'] in ("x86", "arm"): 17110120Snilay@cs.wisc.edu cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave 17210120Snilay@cs.wisc.edu cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave 17310119Snilay@cs.wisc.edu 17411598Sandreas.sandberg@arm.com if buildEnv['TARGET_ISA'] in "x86": 17511150Smitch.hayenga@arm.com cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master 17611150Smitch.hayenga@arm.com cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave 17711150Smitch.hayenga@arm.com cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master 17810119Snilay@cs.wisc.edu 1792995SN/A else: 18010119Snilay@cs.wisc.edu if options.caches or options.l2cache: 18110119Snilay@cs.wisc.edu # By default the IOCache runs at the system clock 18210119Snilay@cs.wisc.edu test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges) 18310119Snilay@cs.wisc.edu test_sys.iocache.cpu_side = test_sys.iobus.master 18410119Snilay@cs.wisc.edu test_sys.iocache.mem_side = test_sys.membus.slave 18510780SCurtis.Dunham@arm.com elif not options.external_memory_system: 18610119Snilay@cs.wisc.edu test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) 18710119Snilay@cs.wisc.edu test_sys.iobridge.slave = test_sys.iobus.master 18810119Snilay@cs.wisc.edu test_sys.iobridge.master = test_sys.membus.slave 1893304Sstever@eecs.umich.edu 19010119Snilay@cs.wisc.edu # Sanity check 19110608Sdam.sunwoo@arm.com if options.simpoint_profile: 19213684Sgiacomo.travaglini@arm.com if not CpuConfig.is_noncaching_cpu(TestCPUClass): 19313012Sandreas.sandberg@arm.com fatal("SimPoint generation should be done with atomic cpu") 19410608Sdam.sunwoo@arm.com if np > 1: 19510608Sdam.sunwoo@arm.com fatal("SimPoint generation not supported with more than one CPUs") 19610608Sdam.sunwoo@arm.com 19710119Snilay@cs.wisc.edu for i in xrange(np): 19810608Sdam.sunwoo@arm.com if options.simpoint_profile: 19910608Sdam.sunwoo@arm.com test_sys.cpu[i].addSimPointProbe(options.simpoint_interval) 20010119Snilay@cs.wisc.edu if options.checker: 20110119Snilay@cs.wisc.edu test_sys.cpu[i].addCheckerCpu() 20213432Spau.cabre@metempsy.com if options.bp_type: 20313432Spau.cabre@metempsy.com bpClass = BPConfig.get(options.bp_type) 20413432Spau.cabre@metempsy.com test_sys.cpu[i].branchPred = bpClass() 20510119Snilay@cs.wisc.edu test_sys.cpu[i].createThreads() 2063819Shsul@eecs.umich.edu 20711251Sradhika.jagtap@ARM.com # If elastic tracing is enabled when not restoring from checkpoint and 20811251Sradhika.jagtap@ARM.com # when not fast forwarding using the atomic cpu, then check that the 20911251Sradhika.jagtap@ARM.com # TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check 21011251Sradhika.jagtap@ARM.com # passes then attach the elastic trace probe. 21111251Sradhika.jagtap@ARM.com # If restoring from checkpoint or fast forwarding, the code that does this for 21211251Sradhika.jagtap@ARM.com # FutureCPUClass is in the Simulation module. If the check passes then the 21311251Sradhika.jagtap@ARM.com # elastic trace probe is attached to the switch CPUs. 21411251Sradhika.jagtap@ARM.com if options.elastic_trace_en and options.checkpoint_restore == None and \ 21511251Sradhika.jagtap@ARM.com not options.fast_forward: 21611251Sradhika.jagtap@ARM.com CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options) 21711251Sradhika.jagtap@ARM.com 21810119Snilay@cs.wisc.edu CacheConfig.config_cache(options, test_sys) 21911183Serfan.azarkhish@unibo.it 22010119Snilay@cs.wisc.edu MemConfig.config_mem(options, test_sys) 22110118Snilay@cs.wisc.edu 22210119Snilay@cs.wisc.edu return test_sys 2239827Sakash.bagdia@arm.com 22410119Snilay@cs.wisc.edudef build_drive_system(np): 22510119Snilay@cs.wisc.edu # driver system CPU is always simple, so is the memory 22610119Snilay@cs.wisc.edu # Note this is an assignment of a class, not an instance. 22710119Snilay@cs.wisc.edu DriveCPUClass = AtomicSimpleCPU 22810119Snilay@cs.wisc.edu drive_mem_mode = 'atomic' 22910119Snilay@cs.wisc.edu DriveMemClass = SimpleMemory 2309827Sakash.bagdia@arm.com 23110594Sgabeblack@google.com cmdline = cmd_line_template() 2326654Snate@binkert.org if buildEnv['TARGET_ISA'] == 'alpha': 23310594Sgabeblack@google.com drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1], cmdline=cmdline) 2346654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'mips': 23510594Sgabeblack@google.com drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1], cmdline=cmdline) 2366654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'sparc': 23710594Sgabeblack@google.com drive_sys = makeSparcSystem(drive_mem_mode, bm[1], cmdline=cmdline) 2386654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'x86': 23910594Sgabeblack@google.com drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1], 24010594Sgabeblack@google.com cmdline=cmdline) 2417586SAli.Saidi@arm.com elif buildEnv['TARGET_ISA'] == 'arm': 24210635Satgutier@umich.edu drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, np, 24313606Sciro.santilli@arm.com bm[1], options.dtb_filename, cmdline=cmdline) 2448661SAli.Saidi@ARM.com 2459827Sakash.bagdia@arm.com # Create a top-level voltage domain 2469827Sakash.bagdia@arm.com drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 2479827Sakash.bagdia@arm.com 2489793Sakash.bagdia@arm.com # Create a source clock for the system and set the clock period 24910119Snilay@cs.wisc.edu drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, 25010119Snilay@cs.wisc.edu voltage_domain = drive_sys.voltage_domain) 2519790Sakash.bagdia@arm.com 2529827Sakash.bagdia@arm.com # Create a CPU voltage domain 2539827Sakash.bagdia@arm.com drive_sys.cpu_voltage_domain = VoltageDomain() 2549827Sakash.bagdia@arm.com 2559793Sakash.bagdia@arm.com # Create a source clock for the CPUs and set the clock period 2569827Sakash.bagdia@arm.com drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 2579827Sakash.bagdia@arm.com voltage_domain = 2589827Sakash.bagdia@arm.com drive_sys.cpu_voltage_domain) 2599793Sakash.bagdia@arm.com 2609793Sakash.bagdia@arm.com drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain, 2619793Sakash.bagdia@arm.com cpu_id=0) 2629384SAndreas.Sandberg@arm.com drive_sys.cpu.createThreads() 2638863Snilay@cs.wisc.edu drive_sys.cpu.createInterruptController() 2647876Sgblack@eecs.umich.edu drive_sys.cpu.connectAllPorts(drive_sys.membus) 2654837Ssaidi@eecs.umich.edu if options.kernel is not None: 2664837Ssaidi@eecs.umich.edu drive_sys.kernel = binary(options.kernel) 2679408Sandreas.hansson@arm.com 26812941Sandreas.sandberg@arm.com if CpuConfig.is_kvm_cpu(DriveCPUClass): 26911839SCurtis.Dunham@arm.com drive_sys.kvm_vm = KvmVM() 2709653SAndreas.Sandberg@ARM.com 2719164Sandreas.hansson@arm.com drive_sys.iobridge = Bridge(delay='50ns', 2729408Sandreas.hansson@arm.com ranges = drive_sys.mem_ranges) 2738845Sandreas.hansson@arm.com drive_sys.iobridge.slave = drive_sys.iobus.master 2748845Sandreas.hansson@arm.com drive_sys.iobridge.master = drive_sys.membus.slave 2754837Ssaidi@eecs.umich.edu 2769826Sandreas.hansson@arm.com # Create the appropriate memory controllers and connect them to the 2779826Sandreas.hansson@arm.com # memory bus 2789835Sandreas.hansson@arm.com drive_sys.mem_ctrls = [DriveMemClass(range = r) 2799826Sandreas.hansson@arm.com for r in drive_sys.mem_ranges] 2809826Sandreas.hansson@arm.com for i in xrange(len(drive_sys.mem_ctrls)): 2819826Sandreas.hansson@arm.com drive_sys.mem_ctrls[i].port = drive_sys.membus.master 2829826Sandreas.hansson@arm.com 2838659SAli.Saidi@ARM.com drive_sys.init_param = options.init_param 28410119Snilay@cs.wisc.edu 28510119Snilay@cs.wisc.edu return drive_sys 28610119Snilay@cs.wisc.edu 28710119Snilay@cs.wisc.edu# Add options 28810119Snilay@cs.wisc.eduparser = optparse.OptionParser() 28910119Snilay@cs.wisc.eduOptions.addCommonOptions(parser) 29010119Snilay@cs.wisc.eduOptions.addFSOptions(parser) 29110119Snilay@cs.wisc.edu 29210119Snilay@cs.wisc.edu# Add the ruby specific and protocol specific options 29310119Snilay@cs.wisc.eduif '--ruby' in sys.argv: 29410119Snilay@cs.wisc.edu Ruby.define_options(parser) 29510119Snilay@cs.wisc.edu 29610119Snilay@cs.wisc.edu(options, args) = parser.parse_args() 29710119Snilay@cs.wisc.edu 29810119Snilay@cs.wisc.eduif args: 29912564Sgabeblack@google.com print("Error: script doesn't take any positional arguments") 30010119Snilay@cs.wisc.edu sys.exit(1) 30110119Snilay@cs.wisc.edu 30210119Snilay@cs.wisc.edu# system under test can be any CPU 30310119Snilay@cs.wisc.edu(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 30410119Snilay@cs.wisc.edu 30510119Snilay@cs.wisc.edu# Match the memories with the CPUs, based on the options for the test system 30610119Snilay@cs.wisc.eduTestMemClass = Simulation.setMemClass(options) 30710119Snilay@cs.wisc.edu 30810119Snilay@cs.wisc.eduif options.benchmark: 30910119Snilay@cs.wisc.edu try: 31010119Snilay@cs.wisc.edu bm = Benchmarks[options.benchmark] 31110119Snilay@cs.wisc.edu except KeyError: 31212564Sgabeblack@google.com print("Error benchmark %s has not been defined." % options.benchmark) 31312564Sgabeblack@google.com print("Valid benchmarks are: %s" % DefinedBenchmarks) 31410119Snilay@cs.wisc.edu sys.exit(1) 31510119Snilay@cs.wisc.eduelse: 31610119Snilay@cs.wisc.edu if options.dual: 31710697SCurtis.Dunham@arm.com bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device, 31810747SChris.Emmons@arm.com mem=options.mem_size, os_type=options.os_type), 31910697SCurtis.Dunham@arm.com SysConfig(disk=options.disk_image, rootdev=options.root_device, 32010747SChris.Emmons@arm.com mem=options.mem_size, os_type=options.os_type)] 32110119Snilay@cs.wisc.edu else: 32210697SCurtis.Dunham@arm.com bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device, 32310747SChris.Emmons@arm.com mem=options.mem_size, os_type=options.os_type)] 32410119Snilay@cs.wisc.edu 32510119Snilay@cs.wisc.edunp = options.num_cpus 32610119Snilay@cs.wisc.edu 32710119Snilay@cs.wisc.edutest_sys = build_test_system(np) 32810119Snilay@cs.wisc.eduif len(bm) == 2: 32910119Snilay@cs.wisc.edu drive_sys = build_drive_system(np) 3308801Sgblack@eecs.umich.edu root = makeDualRoot(True, test_sys, drive_sys, options.etherdump) 33111291Sgabor.dozsa@arm.comelif len(bm) == 1 and options.dist: 33211291Sgabor.dozsa@arm.com # This system is part of a dist-gem5 simulation 33311291Sgabor.dozsa@arm.com root = makeDistRoot(test_sys, 33411291Sgabor.dozsa@arm.com options.dist_rank, 33511291Sgabor.dozsa@arm.com options.dist_size, 33611291Sgabor.dozsa@arm.com options.dist_server_name, 33711291Sgabor.dozsa@arm.com options.dist_server_port, 33811291Sgabor.dozsa@arm.com options.dist_sync_repeat, 33911291Sgabor.dozsa@arm.com options.dist_sync_start, 34011291Sgabor.dozsa@arm.com options.ethernet_linkspeed, 34111291Sgabor.dozsa@arm.com options.ethernet_linkdelay, 34211291Sgabor.dozsa@arm.com options.etherdump); 3433005Sstever@eecs.umich.eduelif len(bm) == 1: 3448801Sgblack@eecs.umich.edu root = Root(full_system=True, system=test_sys) 3453005Sstever@eecs.umich.eduelse: 34612564Sgabeblack@google.com print("Error I don't know how to create more than 2 systems.") 3473005Sstever@eecs.umich.edu sys.exit(1) 3482566SN/A 3497861Sgblack@eecs.umich.eduif options.timesync: 3507861Sgblack@eecs.umich.edu root.time_sync_enable = True 3517861Sgblack@eecs.umich.edu 3528635Schris.emmons@arm.comif options.frame_capture: 3538635Schris.emmons@arm.com VncServer.frame_capture = True 3548635Schris.emmons@arm.com 35513606Sciro.santilli@arm.comif buildEnv['TARGET_ISA'] == "arm" and not options.bare_metal \ 35613606Sciro.santilli@arm.com and not options.dtb_filename: 35712475Sglenn.bergmans@arm.com if options.machine_type not in ["VExpress_GEM5", "VExpress_GEM5_V1"]: 35812475Sglenn.bergmans@arm.com warn("Can only correctly generate a dtb for VExpress_GEM5_V1 " \ 35912475Sglenn.bergmans@arm.com "platforms, unless custom hardware models have been equipped "\ 36012475Sglenn.bergmans@arm.com "with generation functionality.") 36112475Sglenn.bergmans@arm.com 36212475Sglenn.bergmans@arm.com # Generate a Device Tree 36312475Sglenn.bergmans@arm.com for sysname in ('system', 'testsys', 'drivesys'): 36412475Sglenn.bergmans@arm.com if hasattr(root, sysname): 36512475Sglenn.bergmans@arm.com sys = getattr(root, sysname) 36613608Sgiacomo.travaglini@arm.com sys.generateDtb(m5.options.outdir, '%s.dtb' % sysname) 36712475Sglenn.bergmans@arm.com 3689061Snilay@cs.wisc.eduSimulation.setWorkCountOptions(test_sys, options) 3693481Shsul@eecs.umich.eduSimulation.run(options, root, test_sys, FutureClass) 370