fs.py revision 12598
17119Sgblack@eecs.umich.edu# Copyright (c) 2010-2013, 2016 ARM Limited 27119Sgblack@eecs.umich.edu# All rights reserved. 37120Sgblack@eecs.umich.edu# 47120Sgblack@eecs.umich.edu# The license below extends only to copyright in the software and shall 57120Sgblack@eecs.umich.edu# not be construed as granting a license to any other intellectual 67120Sgblack@eecs.umich.edu# property including but not limited to intellectual property relating 77120Sgblack@eecs.umich.edu# to a hardware implementation of the functionality of the software 87120Sgblack@eecs.umich.edu# licensed hereunder. You may use the software subject to the license 97120Sgblack@eecs.umich.edu# terms below provided that you ensure that this notice is replicated 107120Sgblack@eecs.umich.edu# unmodified and in its entirety in all distributions of the software, 117120Sgblack@eecs.umich.edu# modified or unmodified, in source code or in binary form. 127120Sgblack@eecs.umich.edu# 137120Sgblack@eecs.umich.edu# Copyright (c) 2012-2014 Mark D. Hill and David A. Wood 147120Sgblack@eecs.umich.edu# Copyright (c) 2009-2011 Advanced Micro Devices, Inc. 157119Sgblack@eecs.umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 167119Sgblack@eecs.umich.edu# All rights reserved. 177119Sgblack@eecs.umich.edu# 187119Sgblack@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 197119Sgblack@eecs.umich.edu# modification, are permitted provided that the following conditions are 207119Sgblack@eecs.umich.edu# met: redistributions of source code must retain the above copyright 217119Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 227119Sgblack@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 237119Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 247119Sgblack@eecs.umich.edu# documentation and/or other materials provided with the distribution; 257119Sgblack@eecs.umich.edu# neither the name of the copyright holders nor the names of its 267119Sgblack@eecs.umich.edu# contributors may be used to endorse or promote products derived from 277119Sgblack@eecs.umich.edu# this software without specific prior written permission. 287119Sgblack@eecs.umich.edu# 297119Sgblack@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 307119Sgblack@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 317119Sgblack@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 327119Sgblack@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 337119Sgblack@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 347119Sgblack@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 357119Sgblack@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 367119Sgblack@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 377119Sgblack@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 387119Sgblack@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 397119Sgblack@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 407119Sgblack@eecs.umich.edu# 417119Sgblack@eecs.umich.edu# Authors: Ali Saidi 427119Sgblack@eecs.umich.edu# Brad Beckmann 437119Sgblack@eecs.umich.edu 447205Sgblack@eecs.umich.edufrom __future__ import print_function 457205Sgblack@eecs.umich.edu 467205Sgblack@eecs.umich.eduimport optparse 477205Sgblack@eecs.umich.eduimport sys 487205Sgblack@eecs.umich.edu 497205Sgblack@eecs.umich.eduimport m5 507205Sgblack@eecs.umich.edufrom m5.defines import buildEnv 517205Sgblack@eecs.umich.edufrom m5.objects import * 527205Sgblack@eecs.umich.edufrom m5.util import addToPath, fatal, warn 537205Sgblack@eecs.umich.edufrom m5.util.fdthelper import * 547205Sgblack@eecs.umich.edu 557205Sgblack@eecs.umich.eduaddToPath('../') 567205Sgblack@eecs.umich.edu 577205Sgblack@eecs.umich.edufrom ruby import Ruby 587205Sgblack@eecs.umich.edu 597205Sgblack@eecs.umich.edufrom common.FSConfig import * 607205Sgblack@eecs.umich.edufrom common.SysPaths import * 617205Sgblack@eecs.umich.edufrom common.Benchmarks import * 627205Sgblack@eecs.umich.edufrom common import Simulation 637205Sgblack@eecs.umich.edufrom common import CacheConfig 647205Sgblack@eecs.umich.edufrom common import MemConfig 657205Sgblack@eecs.umich.edufrom common import CpuConfig 667205Sgblack@eecs.umich.edufrom common.Caches import * 677205Sgblack@eecs.umich.edufrom common import Options 687205Sgblack@eecs.umich.edu 697205Sgblack@eecs.umich.edu 707205Sgblack@eecs.umich.edu# Check if KVM support has been enabled, we might need to do VM 717205Sgblack@eecs.umich.edu# configuration if that's the case. 727597Sminkyu.jeong@arm.comhave_kvm_support = 'BaseKvmCPU' in globals() 737597Sminkyu.jeong@arm.comdef is_kvm_cpu(cpu_class): 747205Sgblack@eecs.umich.edu return have_kvm_support and cpu_class != None and \ 757205Sgblack@eecs.umich.edu issubclass(cpu_class, BaseKvmCPU) 767408Sgblack@eecs.umich.edu 777408Sgblack@eecs.umich.edudef cmd_line_template(): 787408Sgblack@eecs.umich.edu if options.command_line and options.command_line_file: 797408Sgblack@eecs.umich.edu print("Error: --command-line and --command-line-file are " 807205Sgblack@eecs.umich.edu "mutually exclusive") 817205Sgblack@eecs.umich.edu sys.exit(1) 827205Sgblack@eecs.umich.edu if options.command_line: 837205Sgblack@eecs.umich.edu return options.command_line 847205Sgblack@eecs.umich.edu if options.command_line_file: 857205Sgblack@eecs.umich.edu return open(options.command_line_file).read().strip() 867205Sgblack@eecs.umich.edu return None 877205Sgblack@eecs.umich.edu 887205Sgblack@eecs.umich.edudef build_test_system(np): 897205Sgblack@eecs.umich.edu cmdline = cmd_line_template() 907205Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] == "alpha": 917205Sgblack@eecs.umich.edu test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby, 927205Sgblack@eecs.umich.edu cmdline=cmdline) 937205Sgblack@eecs.umich.edu elif buildEnv['TARGET_ISA'] == "mips": 947205Sgblack@eecs.umich.edu test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline) 957205Sgblack@eecs.umich.edu elif buildEnv['TARGET_ISA'] == "sparc": 967205Sgblack@eecs.umich.edu test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline) 977205Sgblack@eecs.umich.edu elif buildEnv['TARGET_ISA'] == "x86": 987205Sgblack@eecs.umich.edu test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0], 997205Sgblack@eecs.umich.edu options.ruby, cmdline=cmdline) 1007205Sgblack@eecs.umich.edu elif buildEnv['TARGET_ISA'] == "arm": 1017205Sgblack@eecs.umich.edu test_sys = makeArmSystem(test_mem_mode, options.machine_type, 1027205Sgblack@eecs.umich.edu options.num_cpus, bm[0], options.dtb_filename, 1037205Sgblack@eecs.umich.edu bare_metal=options.bare_metal, 1047205Sgblack@eecs.umich.edu cmdline=cmdline, 1057205Sgblack@eecs.umich.edu ignore_dtb=options.generate_dtb, 1067205Sgblack@eecs.umich.edu external_memory= 1077205Sgblack@eecs.umich.edu options.external_memory_system, 1087597Sminkyu.jeong@arm.com ruby=options.ruby, 1097597Sminkyu.jeong@arm.com security=options.enable_security_extensions) 1107205Sgblack@eecs.umich.edu if options.enable_context_switch_stats_dump: 1117205Sgblack@eecs.umich.edu test_sys.enable_context_switch_stats_dump = True 1127408Sgblack@eecs.umich.edu else: 1137408Sgblack@eecs.umich.edu fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) 1147408Sgblack@eecs.umich.edu 1157408Sgblack@eecs.umich.edu # Set the cache line size for the entire system 1167205Sgblack@eecs.umich.edu test_sys.cache_line_size = options.cacheline_size 1177205Sgblack@eecs.umich.edu 1187205Sgblack@eecs.umich.edu # Create a top-level voltage domain 1197205Sgblack@eecs.umich.edu test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 1207205Sgblack@eecs.umich.edu 1217205Sgblack@eecs.umich.edu # Create a source clock for the system and set the clock period 1227205Sgblack@eecs.umich.edu test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, 1237205Sgblack@eecs.umich.edu voltage_domain = test_sys.voltage_domain) 1247205Sgblack@eecs.umich.edu 1257205Sgblack@eecs.umich.edu # Create a CPU voltage domain 1267205Sgblack@eecs.umich.edu test_sys.cpu_voltage_domain = VoltageDomain() 1277205Sgblack@eecs.umich.edu 1287205Sgblack@eecs.umich.edu # Create a source clock for the CPUs and set the clock period 1297205Sgblack@eecs.umich.edu test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 1307205Sgblack@eecs.umich.edu voltage_domain = 1317205Sgblack@eecs.umich.edu test_sys.cpu_voltage_domain) 1327205Sgblack@eecs.umich.edu 1337205Sgblack@eecs.umich.edu if options.kernel is not None: 1347205Sgblack@eecs.umich.edu test_sys.kernel = binary(options.kernel) 1357205Sgblack@eecs.umich.edu 1367205Sgblack@eecs.umich.edu if options.script is not None: 1377205Sgblack@eecs.umich.edu test_sys.readfile = options.script 1387205Sgblack@eecs.umich.edu 1397205Sgblack@eecs.umich.edu if options.lpae: 1407205Sgblack@eecs.umich.edu test_sys.have_lpae = True 1417205Sgblack@eecs.umich.edu 1427408Sgblack@eecs.umich.edu if options.virtualisation: 1437408Sgblack@eecs.umich.edu test_sys.have_virtualization = True 1447408Sgblack@eecs.umich.edu 1457408Sgblack@eecs.umich.edu test_sys.init_param = options.init_param 1467205Sgblack@eecs.umich.edu 1477205Sgblack@eecs.umich.edu # For now, assign all the CPUs to the same clock domain 1487205Sgblack@eecs.umich.edu test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) 1497205Sgblack@eecs.umich.edu for i in xrange(np)] 1507119Sgblack@eecs.umich.edu 1517119Sgblack@eecs.umich.edu if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass): 1527119Sgblack@eecs.umich.edu test_sys.kvm_vm = KvmVM() 1537119Sgblack@eecs.umich.edu 1547119Sgblack@eecs.umich.edu if options.ruby: 1557119Sgblack@eecs.umich.edu bootmem = getattr(test_sys, 'bootmem', None) 1567119Sgblack@eecs.umich.edu Ruby.create_system(options, True, test_sys, test_sys.iobus, 1577119Sgblack@eecs.umich.edu test_sys._dma_ports, bootmem) 1587119Sgblack@eecs.umich.edu 1597119Sgblack@eecs.umich.edu # Create a seperate clock domain for Ruby 1607119Sgblack@eecs.umich.edu test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 1617119Sgblack@eecs.umich.edu voltage_domain = test_sys.voltage_domain) 1627119Sgblack@eecs.umich.edu 1637119Sgblack@eecs.umich.edu # Connect the ruby io port to the PIO bus, 1647119Sgblack@eecs.umich.edu # assuming that there is just one such port. 1657119Sgblack@eecs.umich.edu test_sys.iobus.master = test_sys.ruby._io_port.slave 1667119Sgblack@eecs.umich.edu 1677119Sgblack@eecs.umich.edu for (i, cpu) in enumerate(test_sys.cpu): 1687119Sgblack@eecs.umich.edu # 1697119Sgblack@eecs.umich.edu # Tie the cpu ports to the correct ruby system ports 1707119Sgblack@eecs.umich.edu # 1717597Sminkyu.jeong@arm.com cpu.clk_domain = test_sys.cpu_clk_domain 1727597Sminkyu.jeong@arm.com cpu.createThreads() 1737119Sgblack@eecs.umich.edu cpu.createInterruptController() 1747119Sgblack@eecs.umich.edu 1757408Sgblack@eecs.umich.edu cpu.icache_port = test_sys.ruby._cpu_ports[i].slave 1767408Sgblack@eecs.umich.edu cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave 1777408Sgblack@eecs.umich.edu 1787408Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] in ("x86", "arm"): 1797119Sgblack@eecs.umich.edu cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave 1807119Sgblack@eecs.umich.edu cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave 1817119Sgblack@eecs.umich.edu 1827119Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] in "x86": 1837120Sgblack@eecs.umich.edu cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master 1847120Sgblack@eecs.umich.edu cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave 1857120Sgblack@eecs.umich.edu cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master 1867120Sgblack@eecs.umich.edu 1877120Sgblack@eecs.umich.edu else: 1887120Sgblack@eecs.umich.edu if options.caches or options.l2cache: 1897120Sgblack@eecs.umich.edu # By default the IOCache runs at the system clock 1907120Sgblack@eecs.umich.edu test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges) 1917120Sgblack@eecs.umich.edu test_sys.iocache.cpu_side = test_sys.iobus.master 1927120Sgblack@eecs.umich.edu test_sys.iocache.mem_side = test_sys.membus.slave 1937120Sgblack@eecs.umich.edu elif not options.external_memory_system: 1947120Sgblack@eecs.umich.edu test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) 1957120Sgblack@eecs.umich.edu test_sys.iobridge.slave = test_sys.iobus.master 1967120Sgblack@eecs.umich.edu test_sys.iobridge.master = test_sys.membus.slave 1977120Sgblack@eecs.umich.edu 1987120Sgblack@eecs.umich.edu # Sanity check 1997120Sgblack@eecs.umich.edu if options.fastmem: 2007120Sgblack@eecs.umich.edu if TestCPUClass != AtomicSimpleCPU: 2017120Sgblack@eecs.umich.edu fatal("Fastmem can only be used with atomic CPU!") 2027120Sgblack@eecs.umich.edu if (options.caches or options.l2cache): 2037120Sgblack@eecs.umich.edu fatal("You cannot use fastmem in combination with caches!") 2047120Sgblack@eecs.umich.edu 2057120Sgblack@eecs.umich.edu if options.simpoint_profile: 2067120Sgblack@eecs.umich.edu if not options.fastmem: 2077120Sgblack@eecs.umich.edu # Atomic CPU checked with fastmem option already 2087120Sgblack@eecs.umich.edu fatal("SimPoint generation should be done with atomic cpu and fastmem") 2097597Sminkyu.jeong@arm.com if np > 1: 2107597Sminkyu.jeong@arm.com fatal("SimPoint generation not supported with more than one CPUs") 2117120Sgblack@eecs.umich.edu 2127120Sgblack@eecs.umich.edu for i in xrange(np): 2137408Sgblack@eecs.umich.edu if options.fastmem: 2147408Sgblack@eecs.umich.edu test_sys.cpu[i].fastmem = True 2157408Sgblack@eecs.umich.edu if options.simpoint_profile: 2167408Sgblack@eecs.umich.edu test_sys.cpu[i].addSimPointProbe(options.simpoint_interval) 2177120Sgblack@eecs.umich.edu if options.checker: 2187120Sgblack@eecs.umich.edu test_sys.cpu[i].addCheckerCpu() 2197120Sgblack@eecs.umich.edu test_sys.cpu[i].createThreads() 2207120Sgblack@eecs.umich.edu 2217303Sgblack@eecs.umich.edu # If elastic tracing is enabled when not restoring from checkpoint and 2227303Sgblack@eecs.umich.edu # when not fast forwarding using the atomic cpu, then check that the 2237303Sgblack@eecs.umich.edu # TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check 2247303Sgblack@eecs.umich.edu # passes then attach the elastic trace probe. 2257303Sgblack@eecs.umich.edu # If restoring from checkpoint or fast forwarding, the code that does this for 2267303Sgblack@eecs.umich.edu # FutureCPUClass is in the Simulation module. If the check passes then the 2277303Sgblack@eecs.umich.edu # elastic trace probe is attached to the switch CPUs. 2287303Sgblack@eecs.umich.edu if options.elastic_trace_en and options.checkpoint_restore == None and \ 2297303Sgblack@eecs.umich.edu not options.fast_forward: 2307303Sgblack@eecs.umich.edu CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options) 2317303Sgblack@eecs.umich.edu 2327303Sgblack@eecs.umich.edu CacheConfig.config_cache(options, test_sys) 2337303Sgblack@eecs.umich.edu 2347303Sgblack@eecs.umich.edu MemConfig.config_mem(options, test_sys) 2357303Sgblack@eecs.umich.edu 2367303Sgblack@eecs.umich.edu return test_sys 2377303Sgblack@eecs.umich.edu 2387303Sgblack@eecs.umich.edudef build_drive_system(np): 2397303Sgblack@eecs.umich.edu # driver system CPU is always simple, so is the memory 2407303Sgblack@eecs.umich.edu # Note this is an assignment of a class, not an instance. 2417303Sgblack@eecs.umich.edu DriveCPUClass = AtomicSimpleCPU 2427303Sgblack@eecs.umich.edu drive_mem_mode = 'atomic' 2437303Sgblack@eecs.umich.edu DriveMemClass = SimpleMemory 2447303Sgblack@eecs.umich.edu 2457303Sgblack@eecs.umich.edu cmdline = cmd_line_template() 2467303Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] == 'alpha': 2477303Sgblack@eecs.umich.edu drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1], cmdline=cmdline) 2487303Sgblack@eecs.umich.edu elif buildEnv['TARGET_ISA'] == 'mips': 2497303Sgblack@eecs.umich.edu drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1], cmdline=cmdline) 2507303Sgblack@eecs.umich.edu elif buildEnv['TARGET_ISA'] == 'sparc': 2517303Sgblack@eecs.umich.edu drive_sys = makeSparcSystem(drive_mem_mode, bm[1], cmdline=cmdline) 2527303Sgblack@eecs.umich.edu elif buildEnv['TARGET_ISA'] == 'x86': 2537597Sminkyu.jeong@arm.com drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1], 2547597Sminkyu.jeong@arm.com cmdline=cmdline) 2557303Sgblack@eecs.umich.edu elif buildEnv['TARGET_ISA'] == 'arm': 2567303Sgblack@eecs.umich.edu drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, np, 2577408Sgblack@eecs.umich.edu bm[1], options.dtb_filename, cmdline=cmdline, 2587408Sgblack@eecs.umich.edu ignore_dtb=options.generate_dtb) 2597408Sgblack@eecs.umich.edu 2607408Sgblack@eecs.umich.edu # Create a top-level voltage domain 2617303Sgblack@eecs.umich.edu drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 2627303Sgblack@eecs.umich.edu 2637303Sgblack@eecs.umich.edu # Create a source clock for the system and set the clock period 2647303Sgblack@eecs.umich.edu drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, 2657303Sgblack@eecs.umich.edu voltage_domain = drive_sys.voltage_domain) 2667303Sgblack@eecs.umich.edu 2677303Sgblack@eecs.umich.edu # Create a CPU voltage domain 2687303Sgblack@eecs.umich.edu drive_sys.cpu_voltage_domain = VoltageDomain() 2697303Sgblack@eecs.umich.edu 2707303Sgblack@eecs.umich.edu # Create a source clock for the CPUs and set the clock period 2717303Sgblack@eecs.umich.edu drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 2727303Sgblack@eecs.umich.edu voltage_domain = 2737303Sgblack@eecs.umich.edu drive_sys.cpu_voltage_domain) 2747303Sgblack@eecs.umich.edu 2757303Sgblack@eecs.umich.edu drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain, 2767303Sgblack@eecs.umich.edu cpu_id=0) 2777303Sgblack@eecs.umich.edu drive_sys.cpu.createThreads() 2787303Sgblack@eecs.umich.edu drive_sys.cpu.createInterruptController() 2797303Sgblack@eecs.umich.edu drive_sys.cpu.connectAllPorts(drive_sys.membus) 2807303Sgblack@eecs.umich.edu if options.fastmem: 2817303Sgblack@eecs.umich.edu drive_sys.cpu.fastmem = True 2827303Sgblack@eecs.umich.edu if options.kernel is not None: 2837303Sgblack@eecs.umich.edu drive_sys.kernel = binary(options.kernel) 2847303Sgblack@eecs.umich.edu 2857303Sgblack@eecs.umich.edu if is_kvm_cpu(DriveCPUClass): 2867303Sgblack@eecs.umich.edu drive_sys.kvm_vm = KvmVM() 2877303Sgblack@eecs.umich.edu 2887303Sgblack@eecs.umich.edu drive_sys.iobridge = Bridge(delay='50ns', 2897303Sgblack@eecs.umich.edu ranges = drive_sys.mem_ranges) 2907303Sgblack@eecs.umich.edu drive_sys.iobridge.slave = drive_sys.iobus.master 2917303Sgblack@eecs.umich.edu drive_sys.iobridge.master = drive_sys.membus.slave 2927597Sminkyu.jeong@arm.com 2937597Sminkyu.jeong@arm.com # Create the appropriate memory controllers and connect them to the 2947303Sgblack@eecs.umich.edu # memory bus 2957303Sgblack@eecs.umich.edu drive_sys.mem_ctrls = [DriveMemClass(range = r) 2967408Sgblack@eecs.umich.edu for r in drive_sys.mem_ranges] 2977408Sgblack@eecs.umich.edu for i in xrange(len(drive_sys.mem_ctrls)): 2987408Sgblack@eecs.umich.edu drive_sys.mem_ctrls[i].port = drive_sys.membus.master 2997408Sgblack@eecs.umich.edu 3007303Sgblack@eecs.umich.edu drive_sys.init_param = options.init_param 3017303Sgblack@eecs.umich.edu 3027303Sgblack@eecs.umich.edu return drive_sys 3037303Sgblack@eecs.umich.edu 3047120Sgblack@eecs.umich.edu# Add options 3057120Sgblack@eecs.umich.eduparser = optparse.OptionParser() 3067120Sgblack@eecs.umich.eduOptions.addCommonOptions(parser) 3077120Sgblack@eecs.umich.eduOptions.addFSOptions(parser) 3087120Sgblack@eecs.umich.edu 3097120Sgblack@eecs.umich.edu# Add the ruby specific and protocol specific options 3107120Sgblack@eecs.umich.eduif '--ruby' in sys.argv: 3117120Sgblack@eecs.umich.edu Ruby.define_options(parser) 3127120Sgblack@eecs.umich.edu 3137120Sgblack@eecs.umich.edu(options, args) = parser.parse_args() 3147120Sgblack@eecs.umich.edu 3157120Sgblack@eecs.umich.eduif args: 3167120Sgblack@eecs.umich.edu print("Error: script doesn't take any positional arguments") 3177120Sgblack@eecs.umich.edu sys.exit(1) 3187120Sgblack@eecs.umich.edu 3197120Sgblack@eecs.umich.edu# system under test can be any CPU 3207120Sgblack@eecs.umich.edu(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 3217120Sgblack@eecs.umich.edu 3227120Sgblack@eecs.umich.edu# Match the memories with the CPUs, based on the options for the test system 3237120Sgblack@eecs.umich.eduTestMemClass = Simulation.setMemClass(options) 3247120Sgblack@eecs.umich.edu 3257120Sgblack@eecs.umich.eduif options.benchmark: 3267120Sgblack@eecs.umich.edu try: 3277120Sgblack@eecs.umich.edu bm = Benchmarks[options.benchmark] 3287120Sgblack@eecs.umich.edu except KeyError: 3297120Sgblack@eecs.umich.edu print("Error benchmark %s has not been defined." % options.benchmark) 3307120Sgblack@eecs.umich.edu print("Valid benchmarks are: %s" % DefinedBenchmarks) 3317597Sminkyu.jeong@arm.com sys.exit(1) 3327597Sminkyu.jeong@arm.comelse: 3337120Sgblack@eecs.umich.edu if options.dual: 3347120Sgblack@eecs.umich.edu bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device, 3357408Sgblack@eecs.umich.edu mem=options.mem_size, os_type=options.os_type), 3367408Sgblack@eecs.umich.edu SysConfig(disk=options.disk_image, rootdev=options.root_device, 3377408Sgblack@eecs.umich.edu mem=options.mem_size, os_type=options.os_type)] 3387408Sgblack@eecs.umich.edu else: 3397120Sgblack@eecs.umich.edu bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device, 3407120Sgblack@eecs.umich.edu mem=options.mem_size, os_type=options.os_type)] 3417120Sgblack@eecs.umich.edu 3427120Sgblack@eecs.umich.edunp = options.num_cpus 3437119Sgblack@eecs.umich.edu 3447119Sgblack@eecs.umich.edutest_sys = build_test_system(np) 3457119Sgblack@eecs.umich.eduif len(bm) == 2: 3467119Sgblack@eecs.umich.edu drive_sys = build_drive_system(np) 3477119Sgblack@eecs.umich.edu root = makeDualRoot(True, test_sys, drive_sys, options.etherdump) 3487119Sgblack@eecs.umich.eduelif len(bm) == 1 and options.dist: 3497119Sgblack@eecs.umich.edu # This system is part of a dist-gem5 simulation 3507119Sgblack@eecs.umich.edu root = makeDistRoot(test_sys, 3517119Sgblack@eecs.umich.edu options.dist_rank, 3527119Sgblack@eecs.umich.edu options.dist_size, 3537119Sgblack@eecs.umich.edu options.dist_server_name, 3547119Sgblack@eecs.umich.edu options.dist_server_port, 3557119Sgblack@eecs.umich.edu options.dist_sync_repeat, 3567119Sgblack@eecs.umich.edu options.dist_sync_start, 3577119Sgblack@eecs.umich.edu options.ethernet_linkspeed, 3587119Sgblack@eecs.umich.edu options.ethernet_linkdelay, 3597597Sminkyu.jeong@arm.com options.etherdump); 3607597Sminkyu.jeong@arm.comelif len(bm) == 1: 3617597Sminkyu.jeong@arm.com root = Root(full_system=True, system=test_sys) 3627597Sminkyu.jeong@arm.comelse: 3637597Sminkyu.jeong@arm.com print("Error I don't know how to create more than 2 systems.") 3647119Sgblack@eecs.umich.edu sys.exit(1) 3657119Sgblack@eecs.umich.edu 3667119Sgblack@eecs.umich.eduif options.timesync: 3677119Sgblack@eecs.umich.edu root.time_sync_enable = True 3687119Sgblack@eecs.umich.edu 3697119Sgblack@eecs.umich.eduif options.frame_capture: 3707119Sgblack@eecs.umich.edu VncServer.frame_capture = True 3717119Sgblack@eecs.umich.edu 3727119Sgblack@eecs.umich.eduif buildEnv['TARGET_ISA'] == "arm" and options.generate_dtb: 3737119Sgblack@eecs.umich.edu # Sanity checks 3747119Sgblack@eecs.umich.edu if options.dtb_filename: 3757119Sgblack@eecs.umich.edu fatal("--generate-dtb and --dtb-filename cannot be specified at the"\ 3767119Sgblack@eecs.umich.edu "same time.") 3777119Sgblack@eecs.umich.edu 3787119Sgblack@eecs.umich.edu if options.machine_type not in ["VExpress_GEM5", "VExpress_GEM5_V1"]: 3797119Sgblack@eecs.umich.edu warn("Can only correctly generate a dtb for VExpress_GEM5_V1 " \ 3807119Sgblack@eecs.umich.edu "platforms, unless custom hardware models have been equipped "\ 3817119Sgblack@eecs.umich.edu "with generation functionality.") 3827119Sgblack@eecs.umich.edu 3837119Sgblack@eecs.umich.edu # Generate a Device Tree 3847119Sgblack@eecs.umich.edu def create_dtb_for_system(system, filename): 3857119Sgblack@eecs.umich.edu state = FdtState(addr_cells=2, size_cells=2, cpu_cells=1) 3867119Sgblack@eecs.umich.edu rootNode = system.generateDeviceTree(state) 3877119Sgblack@eecs.umich.edu 3887119Sgblack@eecs.umich.edu fdt = Fdt() 3897119Sgblack@eecs.umich.edu fdt.add_rootnode(rootNode) 3907119Sgblack@eecs.umich.edu dtb_filename = os.path.join(m5.options.outdir, filename) 3917119Sgblack@eecs.umich.edu return fdt.writeDtbFile(dtb_filename) 3927119Sgblack@eecs.umich.edu 3937119Sgblack@eecs.umich.edu for sysname in ('system', 'testsys', 'drivesys'): 3947408Sgblack@eecs.umich.edu if hasattr(root, sysname): 3957408Sgblack@eecs.umich.edu sys = getattr(root, sysname) 3967408Sgblack@eecs.umich.edu sys.dtb_filename = create_dtb_for_system(sys, '%s.dtb' % sysname) 3977408Sgblack@eecs.umich.edu 3987119Sgblack@eecs.umich.eduSimulation.setWorkCountOptions(test_sys, options) 3997119Sgblack@eecs.umich.eduSimulation.run(options, root, test_sys, FutureClass) 4007119Sgblack@eecs.umich.edu