fs.py revision 11598
17119Sgblack@eecs.umich.edu# Copyright (c) 2010-2013, 2016 ARM Limited 27119Sgblack@eecs.umich.edu# All rights reserved. 37120Sgblack@eecs.umich.edu# 47120Sgblack@eecs.umich.edu# The license below extends only to copyright in the software and shall 57120Sgblack@eecs.umich.edu# not be construed as granting a license to any other intellectual 67120Sgblack@eecs.umich.edu# property including but not limited to intellectual property relating 77120Sgblack@eecs.umich.edu# to a hardware implementation of the functionality of the software 87120Sgblack@eecs.umich.edu# licensed hereunder. You may use the software subject to the license 97120Sgblack@eecs.umich.edu# terms below provided that you ensure that this notice is replicated 107120Sgblack@eecs.umich.edu# unmodified and in its entirety in all distributions of the software, 117120Sgblack@eecs.umich.edu# modified or unmodified, in source code or in binary form. 127120Sgblack@eecs.umich.edu# 137120Sgblack@eecs.umich.edu# Copyright (c) 2012-2014 Mark D. Hill and David A. Wood 147120Sgblack@eecs.umich.edu# Copyright (c) 2009-2011 Advanced Micro Devices, Inc. 157119Sgblack@eecs.umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 167119Sgblack@eecs.umich.edu# All rights reserved. 177119Sgblack@eecs.umich.edu# 187119Sgblack@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 197119Sgblack@eecs.umich.edu# modification, are permitted provided that the following conditions are 207119Sgblack@eecs.umich.edu# met: redistributions of source code must retain the above copyright 217119Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 227119Sgblack@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 237119Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 247119Sgblack@eecs.umich.edu# documentation and/or other materials provided with the distribution; 257119Sgblack@eecs.umich.edu# neither the name of the copyright holders nor the names of its 267119Sgblack@eecs.umich.edu# contributors may be used to endorse or promote products derived from 277119Sgblack@eecs.umich.edu# this software without specific prior written permission. 287119Sgblack@eecs.umich.edu# 297119Sgblack@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 307119Sgblack@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 317119Sgblack@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 327119Sgblack@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 337119Sgblack@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 347119Sgblack@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 357119Sgblack@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 367119Sgblack@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 377119Sgblack@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 387119Sgblack@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 397119Sgblack@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 407119Sgblack@eecs.umich.edu# 417119Sgblack@eecs.umich.edu# Authors: Ali Saidi 427119Sgblack@eecs.umich.edu# Brad Beckmann 437119Sgblack@eecs.umich.edu 447205Sgblack@eecs.umich.eduimport optparse 457205Sgblack@eecs.umich.eduimport sys 467205Sgblack@eecs.umich.edu 477205Sgblack@eecs.umich.eduimport m5 487205Sgblack@eecs.umich.edufrom m5.defines import buildEnv 497205Sgblack@eecs.umich.edufrom m5.objects import * 507205Sgblack@eecs.umich.edufrom m5.util import addToPath, fatal 517205Sgblack@eecs.umich.edu 527205Sgblack@eecs.umich.eduaddToPath('../common') 537205Sgblack@eecs.umich.eduaddToPath('../ruby') 547205Sgblack@eecs.umich.edu 557205Sgblack@eecs.umich.eduimport Ruby 567205Sgblack@eecs.umich.edu 577205Sgblack@eecs.umich.edufrom FSConfig import * 587205Sgblack@eecs.umich.edufrom SysPaths import * 597205Sgblack@eecs.umich.edufrom Benchmarks import * 607205Sgblack@eecs.umich.eduimport Simulation 617205Sgblack@eecs.umich.eduimport CacheConfig 627205Sgblack@eecs.umich.eduimport MemConfig 637205Sgblack@eecs.umich.edufrom Caches import * 647205Sgblack@eecs.umich.eduimport Options 657205Sgblack@eecs.umich.edu 667205Sgblack@eecs.umich.edu 677205Sgblack@eecs.umich.edu# Check if KVM support has been enabled, we might need to do VM 687205Sgblack@eecs.umich.edu# configuration if that's the case. 697205Sgblack@eecs.umich.eduhave_kvm_support = 'BaseKvmCPU' in globals() 707205Sgblack@eecs.umich.edudef is_kvm_cpu(cpu_class): 717205Sgblack@eecs.umich.edu return have_kvm_support and cpu_class != None and \ 727205Sgblack@eecs.umich.edu issubclass(cpu_class, BaseKvmCPU) 737205Sgblack@eecs.umich.edu 747205Sgblack@eecs.umich.edudef cmd_line_template(): 757205Sgblack@eecs.umich.edu if options.command_line and options.command_line_file: 767205Sgblack@eecs.umich.edu print "Error: --command-line and --command-line-file are " \ 777205Sgblack@eecs.umich.edu "mutually exclusive" 787205Sgblack@eecs.umich.edu sys.exit(1) 797205Sgblack@eecs.umich.edu if options.command_line: 807205Sgblack@eecs.umich.edu return options.command_line 817205Sgblack@eecs.umich.edu if options.command_line_file: 827205Sgblack@eecs.umich.edu return open(options.command_line_file).read().strip() 837205Sgblack@eecs.umich.edu return None 847205Sgblack@eecs.umich.edu 857205Sgblack@eecs.umich.edudef build_test_system(np): 867205Sgblack@eecs.umich.edu cmdline = cmd_line_template() 877205Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] == "alpha": 887205Sgblack@eecs.umich.edu test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby, 897205Sgblack@eecs.umich.edu cmdline=cmdline) 907205Sgblack@eecs.umich.edu elif buildEnv['TARGET_ISA'] == "mips": 917205Sgblack@eecs.umich.edu test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline) 927205Sgblack@eecs.umich.edu elif buildEnv['TARGET_ISA'] == "sparc": 937205Sgblack@eecs.umich.edu test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline) 947205Sgblack@eecs.umich.edu elif buildEnv['TARGET_ISA'] == "x86": 957205Sgblack@eecs.umich.edu test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0], 967205Sgblack@eecs.umich.edu options.ruby, cmdline=cmdline) 977205Sgblack@eecs.umich.edu elif buildEnv['TARGET_ISA'] == "arm": 987205Sgblack@eecs.umich.edu test_sys = makeArmSystem(test_mem_mode, options.machine_type, 997205Sgblack@eecs.umich.edu options.num_cpus, bm[0], options.dtb_filename, 1007205Sgblack@eecs.umich.edu bare_metal=options.bare_metal, 1017205Sgblack@eecs.umich.edu cmdline=cmdline, 1027205Sgblack@eecs.umich.edu external_memory=options.external_memory_system, 1037205Sgblack@eecs.umich.edu ruby=options.ruby) 1047205Sgblack@eecs.umich.edu if options.enable_context_switch_stats_dump: 1057205Sgblack@eecs.umich.edu test_sys.enable_context_switch_stats_dump = True 1067205Sgblack@eecs.umich.edu else: 1077205Sgblack@eecs.umich.edu fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) 1087205Sgblack@eecs.umich.edu 1097205Sgblack@eecs.umich.edu # Set the cache line size for the entire system 1107205Sgblack@eecs.umich.edu test_sys.cache_line_size = options.cacheline_size 1117205Sgblack@eecs.umich.edu 1127205Sgblack@eecs.umich.edu # Create a top-level voltage domain 1137205Sgblack@eecs.umich.edu test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 1147205Sgblack@eecs.umich.edu 1157205Sgblack@eecs.umich.edu # Create a source clock for the system and set the clock period 1167205Sgblack@eecs.umich.edu test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, 1177205Sgblack@eecs.umich.edu voltage_domain = test_sys.voltage_domain) 1187205Sgblack@eecs.umich.edu 1197205Sgblack@eecs.umich.edu # Create a CPU voltage domain 1207205Sgblack@eecs.umich.edu test_sys.cpu_voltage_domain = VoltageDomain() 1217205Sgblack@eecs.umich.edu 1227205Sgblack@eecs.umich.edu # Create a source clock for the CPUs and set the clock period 1237205Sgblack@eecs.umich.edu test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 1247205Sgblack@eecs.umich.edu voltage_domain = 1257205Sgblack@eecs.umich.edu test_sys.cpu_voltage_domain) 1267205Sgblack@eecs.umich.edu 1277205Sgblack@eecs.umich.edu if options.kernel is not None: 1287205Sgblack@eecs.umich.edu test_sys.kernel = binary(options.kernel) 1297205Sgblack@eecs.umich.edu 1307205Sgblack@eecs.umich.edu if options.script is not None: 1317205Sgblack@eecs.umich.edu test_sys.readfile = options.script 1327205Sgblack@eecs.umich.edu 1337205Sgblack@eecs.umich.edu if options.lpae: 1347119Sgblack@eecs.umich.edu test_sys.have_lpae = True 1357119Sgblack@eecs.umich.edu 1367119Sgblack@eecs.umich.edu if options.virtualisation: 1377119Sgblack@eecs.umich.edu test_sys.have_virtualization = True 1387119Sgblack@eecs.umich.edu 1397119Sgblack@eecs.umich.edu test_sys.init_param = options.init_param 1407119Sgblack@eecs.umich.edu 1417119Sgblack@eecs.umich.edu # For now, assign all the CPUs to the same clock domain 1427119Sgblack@eecs.umich.edu test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) 1437119Sgblack@eecs.umich.edu for i in xrange(np)] 1447119Sgblack@eecs.umich.edu 1457119Sgblack@eecs.umich.edu if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass): 1467119Sgblack@eecs.umich.edu test_sys.vm = KvmVM() 1477119Sgblack@eecs.umich.edu 1487119Sgblack@eecs.umich.edu if options.ruby: 1497119Sgblack@eecs.umich.edu # Check for timing mode because ruby does not support atomic accesses 1507119Sgblack@eecs.umich.edu if not (options.cpu_type == "detailed" or options.cpu_type == "timing"): 1517119Sgblack@eecs.umich.edu print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!" 1527119Sgblack@eecs.umich.edu sys.exit(1) 1537119Sgblack@eecs.umich.edu 1547119Sgblack@eecs.umich.edu Ruby.create_system(options, True, test_sys, test_sys.iobus, 1557119Sgblack@eecs.umich.edu test_sys._dma_ports) 1567119Sgblack@eecs.umich.edu 1577119Sgblack@eecs.umich.edu # Create a seperate clock domain for Ruby 1587119Sgblack@eecs.umich.edu test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 1597119Sgblack@eecs.umich.edu voltage_domain = test_sys.voltage_domain) 1607119Sgblack@eecs.umich.edu 1617120Sgblack@eecs.umich.edu # Connect the ruby io port to the PIO bus, 1627120Sgblack@eecs.umich.edu # assuming that there is just one such port. 1637120Sgblack@eecs.umich.edu test_sys.iobus.master = test_sys.ruby._io_port.slave 1647120Sgblack@eecs.umich.edu 1657120Sgblack@eecs.umich.edu for (i, cpu) in enumerate(test_sys.cpu): 1667120Sgblack@eecs.umich.edu # 1677120Sgblack@eecs.umich.edu # Tie the cpu ports to the correct ruby system ports 1687120Sgblack@eecs.umich.edu # 1697120Sgblack@eecs.umich.edu cpu.clk_domain = test_sys.cpu_clk_domain 1707120Sgblack@eecs.umich.edu cpu.createThreads() 1717120Sgblack@eecs.umich.edu cpu.createInterruptController() 1727120Sgblack@eecs.umich.edu 1737120Sgblack@eecs.umich.edu cpu.icache_port = test_sys.ruby._cpu_ports[i].slave 1747120Sgblack@eecs.umich.edu cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave 1757120Sgblack@eecs.umich.edu 1767120Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] in ("x86", "arm"): 1777120Sgblack@eecs.umich.edu cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave 1787120Sgblack@eecs.umich.edu cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave 1797120Sgblack@eecs.umich.edu 1807120Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] in "x86": 1817120Sgblack@eecs.umich.edu cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master 1827120Sgblack@eecs.umich.edu cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave 1837120Sgblack@eecs.umich.edu cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master 1847120Sgblack@eecs.umich.edu 1857120Sgblack@eecs.umich.edu else: 1867120Sgblack@eecs.umich.edu if options.caches or options.l2cache: 1877120Sgblack@eecs.umich.edu # By default the IOCache runs at the system clock 1887120Sgblack@eecs.umich.edu test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges) 1897120Sgblack@eecs.umich.edu test_sys.iocache.cpu_side = test_sys.iobus.master 1907120Sgblack@eecs.umich.edu test_sys.iocache.mem_side = test_sys.membus.slave 1917120Sgblack@eecs.umich.edu elif not options.external_memory_system: 1927120Sgblack@eecs.umich.edu test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) 1937120Sgblack@eecs.umich.edu test_sys.iobridge.slave = test_sys.iobus.master 1947120Sgblack@eecs.umich.edu test_sys.iobridge.master = test_sys.membus.slave 1957120Sgblack@eecs.umich.edu 1967120Sgblack@eecs.umich.edu # Sanity check 1977120Sgblack@eecs.umich.edu if options.fastmem: 1987120Sgblack@eecs.umich.edu if TestCPUClass != AtomicSimpleCPU: 1997120Sgblack@eecs.umich.edu fatal("Fastmem can only be used with atomic CPU!") 2007120Sgblack@eecs.umich.edu if (options.caches or options.l2cache): 2017120Sgblack@eecs.umich.edu fatal("You cannot use fastmem in combination with caches!") 2027120Sgblack@eecs.umich.edu 2037120Sgblack@eecs.umich.edu if options.simpoint_profile: 2047120Sgblack@eecs.umich.edu if not options.fastmem: 2057120Sgblack@eecs.umich.edu # Atomic CPU checked with fastmem option already 2067120Sgblack@eecs.umich.edu fatal("SimPoint generation should be done with atomic cpu and fastmem") 2077120Sgblack@eecs.umich.edu if np > 1: 2087120Sgblack@eecs.umich.edu fatal("SimPoint generation not supported with more than one CPUs") 2097120Sgblack@eecs.umich.edu 2107120Sgblack@eecs.umich.edu for i in xrange(np): 2117120Sgblack@eecs.umich.edu if options.fastmem: 2127120Sgblack@eecs.umich.edu test_sys.cpu[i].fastmem = True 2137120Sgblack@eecs.umich.edu if options.simpoint_profile: 2147120Sgblack@eecs.umich.edu test_sys.cpu[i].addSimPointProbe(options.simpoint_interval) 2157120Sgblack@eecs.umich.edu if options.checker: 2167120Sgblack@eecs.umich.edu test_sys.cpu[i].addCheckerCpu() 2177120Sgblack@eecs.umich.edu test_sys.cpu[i].createThreads() 2187120Sgblack@eecs.umich.edu 2197120Sgblack@eecs.umich.edu # If elastic tracing is enabled when not restoring from checkpoint and 2207120Sgblack@eecs.umich.edu # when not fast forwarding using the atomic cpu, then check that the 2217120Sgblack@eecs.umich.edu # TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check 2227120Sgblack@eecs.umich.edu # passes then attach the elastic trace probe. 2237120Sgblack@eecs.umich.edu # If restoring from checkpoint or fast forwarding, the code that does this for 2247120Sgblack@eecs.umich.edu # FutureCPUClass is in the Simulation module. If the check passes then the 2257120Sgblack@eecs.umich.edu # elastic trace probe is attached to the switch CPUs. 2267119Sgblack@eecs.umich.edu if options.elastic_trace_en and options.checkpoint_restore == None and \ 2277119Sgblack@eecs.umich.edu not options.fast_forward: 2287119Sgblack@eecs.umich.edu CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options) 2297119Sgblack@eecs.umich.edu 2307119Sgblack@eecs.umich.edu CacheConfig.config_cache(options, test_sys) 2317119Sgblack@eecs.umich.edu 2327119Sgblack@eecs.umich.edu MemConfig.config_mem(options, test_sys) 2337119Sgblack@eecs.umich.edu 2347119Sgblack@eecs.umich.edu return test_sys 2357119Sgblack@eecs.umich.edu 2367119Sgblack@eecs.umich.edudef build_drive_system(np): 2377119Sgblack@eecs.umich.edu # driver system CPU is always simple, so is the memory 2387119Sgblack@eecs.umich.edu # Note this is an assignment of a class, not an instance. 2397119Sgblack@eecs.umich.edu DriveCPUClass = AtomicSimpleCPU 2407119Sgblack@eecs.umich.edu drive_mem_mode = 'atomic' 2417119Sgblack@eecs.umich.edu DriveMemClass = SimpleMemory 2427119Sgblack@eecs.umich.edu 2437119Sgblack@eecs.umich.edu cmdline = cmd_line_template() 2447119Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] == 'alpha': 2457119Sgblack@eecs.umich.edu drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1], cmdline=cmdline) 2467119Sgblack@eecs.umich.edu elif buildEnv['TARGET_ISA'] == 'mips': 2477119Sgblack@eecs.umich.edu drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1], cmdline=cmdline) 2487119Sgblack@eecs.umich.edu elif buildEnv['TARGET_ISA'] == 'sparc': 2497119Sgblack@eecs.umich.edu drive_sys = makeSparcSystem(drive_mem_mode, bm[1], cmdline=cmdline) 2507119Sgblack@eecs.umich.edu elif buildEnv['TARGET_ISA'] == 'x86': 2517119Sgblack@eecs.umich.edu drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1], 2527119Sgblack@eecs.umich.edu cmdline=cmdline) 2537119Sgblack@eecs.umich.edu elif buildEnv['TARGET_ISA'] == 'arm': 2547119Sgblack@eecs.umich.edu drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, np, 2557119Sgblack@eecs.umich.edu bm[1], options.dtb_filename, cmdline=cmdline) 2567119Sgblack@eecs.umich.edu 2577119Sgblack@eecs.umich.edu # Create a top-level voltage domain 2587119Sgblack@eecs.umich.edu drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 2597119Sgblack@eecs.umich.edu 2607119Sgblack@eecs.umich.edu # Create a source clock for the system and set the clock period 2617119Sgblack@eecs.umich.edu drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, 2627119Sgblack@eecs.umich.edu voltage_domain = drive_sys.voltage_domain) 2637119Sgblack@eecs.umich.edu 2647119Sgblack@eecs.umich.edu # Create a CPU voltage domain 2657119Sgblack@eecs.umich.edu drive_sys.cpu_voltage_domain = VoltageDomain() 2667119Sgblack@eecs.umich.edu 2677119Sgblack@eecs.umich.edu # Create a source clock for the CPUs and set the clock period 2687119Sgblack@eecs.umich.edu drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 2697119Sgblack@eecs.umich.edu voltage_domain = 2707119Sgblack@eecs.umich.edu drive_sys.cpu_voltage_domain) 2717119Sgblack@eecs.umich.edu 2727119Sgblack@eecs.umich.edu drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain, 2737119Sgblack@eecs.umich.edu cpu_id=0) 2747119Sgblack@eecs.umich.edu drive_sys.cpu.createThreads() 2757119Sgblack@eecs.umich.edu drive_sys.cpu.createInterruptController() 2767120Sgblack@eecs.umich.edu drive_sys.cpu.connectAllPorts(drive_sys.membus) 2777120Sgblack@eecs.umich.edu if options.fastmem: 2787120Sgblack@eecs.umich.edu drive_sys.cpu.fastmem = True 2797120Sgblack@eecs.umich.edu if options.kernel is not None: 2807120Sgblack@eecs.umich.edu drive_sys.kernel = binary(options.kernel) 2817120Sgblack@eecs.umich.edu 2827120Sgblack@eecs.umich.edu if is_kvm_cpu(DriveCPUClass): 2837120Sgblack@eecs.umich.edu drive_sys.vm = KvmVM() 2847120Sgblack@eecs.umich.edu 2857120Sgblack@eecs.umich.edu drive_sys.iobridge = Bridge(delay='50ns', 2867120Sgblack@eecs.umich.edu ranges = drive_sys.mem_ranges) 2877120Sgblack@eecs.umich.edu drive_sys.iobridge.slave = drive_sys.iobus.master 2887120Sgblack@eecs.umich.edu drive_sys.iobridge.master = drive_sys.membus.slave 2897120Sgblack@eecs.umich.edu 2907120Sgblack@eecs.umich.edu # Create the appropriate memory controllers and connect them to the 2917120Sgblack@eecs.umich.edu # memory bus 2927120Sgblack@eecs.umich.edu drive_sys.mem_ctrls = [DriveMemClass(range = r) 2937120Sgblack@eecs.umich.edu for r in drive_sys.mem_ranges] 2947120Sgblack@eecs.umich.edu for i in xrange(len(drive_sys.mem_ctrls)): 2957120Sgblack@eecs.umich.edu drive_sys.mem_ctrls[i].port = drive_sys.membus.master 2967120Sgblack@eecs.umich.edu 2977205Sgblack@eecs.umich.edu drive_sys.init_param = options.init_param 2987205Sgblack@eecs.umich.edu 2997205Sgblack@eecs.umich.edu return drive_sys 3007205Sgblack@eecs.umich.edu 3017205Sgblack@eecs.umich.edu# Add options 3027205Sgblack@eecs.umich.eduparser = optparse.OptionParser() 3037205Sgblack@eecs.umich.eduOptions.addCommonOptions(parser) 3047205Sgblack@eecs.umich.eduOptions.addFSOptions(parser) 3057205Sgblack@eecs.umich.edu 3067205Sgblack@eecs.umich.edu# Add the ruby specific and protocol specific options 3077205Sgblack@eecs.umich.eduif '--ruby' in sys.argv: 3087205Sgblack@eecs.umich.edu Ruby.define_options(parser) 3097205Sgblack@eecs.umich.edu 3107205Sgblack@eecs.umich.edu(options, args) = parser.parse_args() 3117205Sgblack@eecs.umich.edu 3127205Sgblack@eecs.umich.eduif args: 3137205Sgblack@eecs.umich.edu print "Error: script doesn't take any positional arguments" 3147205Sgblack@eecs.umich.edu sys.exit(1) 3157205Sgblack@eecs.umich.edu 3167205Sgblack@eecs.umich.edu# system under test can be any CPU 3177279Sgblack@eecs.umich.edu(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 3187279Sgblack@eecs.umich.edu 3197279Sgblack@eecs.umich.edu# Match the memories with the CPUs, based on the options for the test system 3207279Sgblack@eecs.umich.eduTestMemClass = Simulation.setMemClass(options) 3217279Sgblack@eecs.umich.edu 3227279Sgblack@eecs.umich.eduif options.benchmark: 3237279Sgblack@eecs.umich.edu try: 3247279Sgblack@eecs.umich.edu bm = Benchmarks[options.benchmark] 3257279Sgblack@eecs.umich.edu except KeyError: 3267279Sgblack@eecs.umich.edu print "Error benchmark %s has not been defined." % options.benchmark 3277279Sgblack@eecs.umich.edu print "Valid benchmarks are: %s" % DefinedBenchmarks 3287279Sgblack@eecs.umich.edu sys.exit(1) 3297279Sgblack@eecs.umich.eduelse: 3307279Sgblack@eecs.umich.edu if options.dual: 3317279Sgblack@eecs.umich.edu bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device, 3327279Sgblack@eecs.umich.edu mem=options.mem_size, os_type=options.os_type), 3337279Sgblack@eecs.umich.edu SysConfig(disk=options.disk_image, rootdev=options.root_device, 3347279Sgblack@eecs.umich.edu mem=options.mem_size, os_type=options.os_type)] 3357279Sgblack@eecs.umich.edu else: 3367279Sgblack@eecs.umich.edu bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device, 3377279Sgblack@eecs.umich.edu mem=options.mem_size, os_type=options.os_type)] 3387119Sgblack@eecs.umich.edu 3397119Sgblack@eecs.umich.edunp = options.num_cpus 3407119Sgblack@eecs.umich.edu 3417119Sgblack@eecs.umich.edutest_sys = build_test_system(np) 3427119Sgblack@eecs.umich.eduif len(bm) == 2: 3437119Sgblack@eecs.umich.edu drive_sys = build_drive_system(np) 3447119Sgblack@eecs.umich.edu root = makeDualRoot(True, test_sys, drive_sys, options.etherdump) 3457119Sgblack@eecs.umich.eduelif len(bm) == 1 and options.dist: 3467119Sgblack@eecs.umich.edu # This system is part of a dist-gem5 simulation 3477119Sgblack@eecs.umich.edu root = makeDistRoot(test_sys, 3487119Sgblack@eecs.umich.edu options.dist_rank, 3497119Sgblack@eecs.umich.edu options.dist_size, 3507119Sgblack@eecs.umich.edu options.dist_server_name, 3517119Sgblack@eecs.umich.edu options.dist_server_port, 3527119Sgblack@eecs.umich.edu options.dist_sync_repeat, 3537119Sgblack@eecs.umich.edu options.dist_sync_start, 3547119Sgblack@eecs.umich.edu options.ethernet_linkspeed, 3557119Sgblack@eecs.umich.edu options.ethernet_linkdelay, 3567119Sgblack@eecs.umich.edu options.etherdump); 3577119Sgblack@eecs.umich.eduelif len(bm) == 1: 3587279Sgblack@eecs.umich.edu root = Root(full_system=True, system=test_sys) 3597279Sgblack@eecs.umich.eduelse: 3607279Sgblack@eecs.umich.edu print "Error I don't know how to create more than 2 systems." 3617279Sgblack@eecs.umich.edu sys.exit(1) 3627279Sgblack@eecs.umich.edu 3637279Sgblack@eecs.umich.eduif options.timesync: 3647279Sgblack@eecs.umich.edu root.time_sync_enable = True 3657279Sgblack@eecs.umich.edu 3667279Sgblack@eecs.umich.eduif options.frame_capture: 3677279Sgblack@eecs.umich.edu VncServer.frame_capture = True 3687279Sgblack@eecs.umich.edu 3697279Sgblack@eecs.umich.eduSimulation.setWorkCountOptions(test_sys, options) 3707279Sgblack@eecs.umich.eduSimulation.run(options, root, test_sys, FutureClass) 3717279Sgblack@eecs.umich.edu