fs.py revision 11291
14120Sgblack@eecs.umich.edu# Copyright (c) 2010-2013 ARM Limited 24120Sgblack@eecs.umich.edu# All rights reserved. 34120Sgblack@eecs.umich.edu# 44120Sgblack@eecs.umich.edu# The license below extends only to copyright in the software and shall 54120Sgblack@eecs.umich.edu# not be construed as granting a license to any other intellectual 64120Sgblack@eecs.umich.edu# property including but not limited to intellectual property relating 74120Sgblack@eecs.umich.edu# to a hardware implementation of the functionality of the software 84120Sgblack@eecs.umich.edu# licensed hereunder. You may use the software subject to the license 94120Sgblack@eecs.umich.edu# terms below provided that you ensure that this notice is replicated 104120Sgblack@eecs.umich.edu# unmodified and in its entirety in all distributions of the software, 114120Sgblack@eecs.umich.edu# modified or unmodified, in source code or in binary form. 124120Sgblack@eecs.umich.edu# 134120Sgblack@eecs.umich.edu# Copyright (c) 2012-2014 Mark D. Hill and David A. Wood 144120Sgblack@eecs.umich.edu# Copyright (c) 2009-2011 Advanced Micro Devices, Inc. 154120Sgblack@eecs.umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 164120Sgblack@eecs.umich.edu# All rights reserved. 174120Sgblack@eecs.umich.edu# 184120Sgblack@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 194120Sgblack@eecs.umich.edu# modification, are permitted provided that the following conditions are 204120Sgblack@eecs.umich.edu# met: redistributions of source code must retain the above copyright 214120Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 224120Sgblack@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 234120Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 244120Sgblack@eecs.umich.edu# documentation and/or other materials provided with the distribution; 254120Sgblack@eecs.umich.edu# neither the name of the copyright holders nor the names of its 264120Sgblack@eecs.umich.edu# contributors may be used to endorse or promote products derived from 274120Sgblack@eecs.umich.edu# this software without specific prior written permission. 284120Sgblack@eecs.umich.edu# 294120Sgblack@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 304120Sgblack@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 314120Sgblack@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 324120Sgblack@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 334120Sgblack@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 344120Sgblack@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 354120Sgblack@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 364120Sgblack@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 374120Sgblack@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 384120Sgblack@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 394120Sgblack@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 404120Sgblack@eecs.umich.edu# 414120Sgblack@eecs.umich.edu# Authors: Ali Saidi 424120Sgblack@eecs.umich.edu# Brad Beckmann 434120Sgblack@eecs.umich.edu 444120Sgblack@eecs.umich.eduimport optparse 454120Sgblack@eecs.umich.eduimport sys 464120Sgblack@eecs.umich.edu 474120Sgblack@eecs.umich.eduimport m5 484120Sgblack@eecs.umich.edufrom m5.defines import buildEnv 494120Sgblack@eecs.umich.edufrom m5.objects import * 504120Sgblack@eecs.umich.edufrom m5.util import addToPath, fatal 514120Sgblack@eecs.umich.edu 524120Sgblack@eecs.umich.eduaddToPath('../common') 534120Sgblack@eecs.umich.eduaddToPath('../ruby') 544120Sgblack@eecs.umich.edu 554120Sgblack@eecs.umich.eduimport Ruby 564120Sgblack@eecs.umich.edu 574120Sgblack@eecs.umich.edufrom FSConfig import * 584120Sgblack@eecs.umich.edufrom SysPaths import * 594120Sgblack@eecs.umich.edufrom Benchmarks import * 604120Sgblack@eecs.umich.eduimport Simulation 614166Sgblack@eecs.umich.eduimport CacheConfig 624166Sgblack@eecs.umich.eduimport MemConfig 634166Sgblack@eecs.umich.edufrom Caches import * 644120Sgblack@eecs.umich.eduimport Options 655956Sgblack@eecs.umich.edu 665956Sgblack@eecs.umich.edu 674120Sgblack@eecs.umich.edu# Check if KVM support has been enabled, we might need to do VM 684120Sgblack@eecs.umich.edu# configuration if that's the case. 697073Sgblack@eecs.umich.eduhave_kvm_support = 'BaseKvmCPU' in globals() 707073Sgblack@eecs.umich.edudef is_kvm_cpu(cpu_class): 717073Sgblack@eecs.umich.edu return have_kvm_support and cpu_class != None and \ 727073Sgblack@eecs.umich.edu issubclass(cpu_class, BaseKvmCPU) 734166Sgblack@eecs.umich.edu 744166Sgblack@eecs.umich.edudef cmd_line_template(): 754166Sgblack@eecs.umich.edu if options.command_line and options.command_line_file: 764166Sgblack@eecs.umich.edu print "Error: --command-line and --command-line-file are " \ 775962Sgblack@eecs.umich.edu "mutually exclusive" 785962Sgblack@eecs.umich.edu sys.exit(1) 795962Sgblack@eecs.umich.edu if options.command_line: 805956Sgblack@eecs.umich.edu return options.command_line 815956Sgblack@eecs.umich.edu if options.command_line_file: 824166Sgblack@eecs.umich.edu return open(options.command_line_file).read().strip() 835956Sgblack@eecs.umich.edu return None 845956Sgblack@eecs.umich.edu 855956Sgblack@eecs.umich.edudef build_test_system(np): 865956Sgblack@eecs.umich.edu cmdline = cmd_line_template() 875973Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] == "alpha": 885973Sgblack@eecs.umich.edu test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby, 894166Sgblack@eecs.umich.edu cmdline=cmdline) 904166Sgblack@eecs.umich.edu elif buildEnv['TARGET_ISA'] == "mips": 915962Sgblack@eecs.umich.edu test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline) 925962Sgblack@eecs.umich.edu elif buildEnv['TARGET_ISA'] == "sparc": 935962Sgblack@eecs.umich.edu test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline) 945962Sgblack@eecs.umich.edu elif buildEnv['TARGET_ISA'] == "x86": 955962Sgblack@eecs.umich.edu test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0], 965962Sgblack@eecs.umich.edu options.ruby, cmdline=cmdline) 975956Sgblack@eecs.umich.edu elif buildEnv['TARGET_ISA'] == "arm": 985958Sgblack@eecs.umich.edu test_sys = makeArmSystem(test_mem_mode, options.machine_type, 995958Sgblack@eecs.umich.edu options.num_cpus, bm[0], options.dtb_filename, 1005956Sgblack@eecs.umich.edu bare_metal=options.bare_metal, 1014166Sgblack@eecs.umich.edu cmdline=cmdline, 1025956Sgblack@eecs.umich.edu external_memory=options.external_memory_system) 1035956Sgblack@eecs.umich.edu if options.enable_context_switch_stats_dump: 1045956Sgblack@eecs.umich.edu test_sys.enable_context_switch_stats_dump = True 1055956Sgblack@eecs.umich.edu else: 1065956Sgblack@eecs.umich.edu fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) 1074166Sgblack@eecs.umich.edu 1086709Svince@csl.cornell.edu # Set the cache line size for the entire system 1096709Svince@csl.cornell.edu test_sys.cache_line_size = options.cacheline_size 1106709Svince@csl.cornell.edu 1116709Svince@csl.cornell.edu # Create a top-level voltage domain 1126709Svince@csl.cornell.edu test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 1136709Svince@csl.cornell.edu 1146709Svince@csl.cornell.edu # Create a source clock for the system and set the clock period 1156709Svince@csl.cornell.edu test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, 1166709Svince@csl.cornell.edu voltage_domain = test_sys.voltage_domain) 1176709Svince@csl.cornell.edu 1185956Sgblack@eecs.umich.edu # Create a CPU voltage domain 1194166Sgblack@eecs.umich.edu test_sys.cpu_voltage_domain = VoltageDomain() 1205956Sgblack@eecs.umich.edu 1215958Sgblack@eecs.umich.edu # Create a source clock for the CPUs and set the clock period 1226701Sgblack@eecs.umich.edu test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 1235958Sgblack@eecs.umich.edu voltage_domain = 1245956Sgblack@eecs.umich.edu test_sys.cpu_voltage_domain) 1255956Sgblack@eecs.umich.edu 1265956Sgblack@eecs.umich.edu if options.kernel is not None: 1275956Sgblack@eecs.umich.edu test_sys.kernel = binary(options.kernel) 1285956Sgblack@eecs.umich.edu 1295956Sgblack@eecs.umich.edu if options.script is not None: 1305956Sgblack@eecs.umich.edu test_sys.readfile = options.script 1315956Sgblack@eecs.umich.edu 1325973Sgblack@eecs.umich.edu if options.lpae: 1335973Sgblack@eecs.umich.edu test_sys.have_lpae = True 1345973Sgblack@eecs.umich.edu 1355973Sgblack@eecs.umich.edu if options.virtualisation: 1365973Sgblack@eecs.umich.edu test_sys.have_virtualization = True 1375973Sgblack@eecs.umich.edu 1385973Sgblack@eecs.umich.edu test_sys.init_param = options.init_param 1395973Sgblack@eecs.umich.edu 1405973Sgblack@eecs.umich.edu # For now, assign all the CPUs to the same clock domain 1415973Sgblack@eecs.umich.edu test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) 1425956Sgblack@eecs.umich.edu for i in xrange(np)] 1435956Sgblack@eecs.umich.edu 1445956Sgblack@eecs.umich.edu if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass): 1455958Sgblack@eecs.umich.edu test_sys.vm = KvmVM() 1465973Sgblack@eecs.umich.edu 1476701Sgblack@eecs.umich.edu if options.ruby: 1486701Sgblack@eecs.umich.edu # Check for timing mode because ruby does not support atomic accesses 1495958Sgblack@eecs.umich.edu if not (options.cpu_type == "detailed" or options.cpu_type == "timing"): 1504166Sgblack@eecs.umich.edu print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!" 1514166Sgblack@eecs.umich.edu sys.exit(1) 1524120Sgblack@eecs.umich.edu 1534120Sgblack@eecs.umich.edu Ruby.create_system(options, True, test_sys, test_sys.iobus, 154 test_sys._dma_ports) 155 156 # Create a seperate clock domain for Ruby 157 test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 158 voltage_domain = test_sys.voltage_domain) 159 160 # Connect the ruby io port to the PIO bus, 161 # assuming that there is just one such port. 162 test_sys.iobus.master = test_sys.ruby._io_port.slave 163 164 for (i, cpu) in enumerate(test_sys.cpu): 165 # 166 # Tie the cpu ports to the correct ruby system ports 167 # 168 cpu.clk_domain = test_sys.cpu_clk_domain 169 cpu.createThreads() 170 cpu.createInterruptController() 171 172 cpu.icache_port = test_sys.ruby._cpu_ports[i].slave 173 cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave 174 175 if buildEnv['TARGET_ISA'] == "x86": 176 cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave 177 cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave 178 179 cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master 180 cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave 181 cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master 182 183 else: 184 if options.caches or options.l2cache: 185 # By default the IOCache runs at the system clock 186 test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges) 187 test_sys.iocache.cpu_side = test_sys.iobus.master 188 test_sys.iocache.mem_side = test_sys.membus.slave 189 elif not options.external_memory_system: 190 test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) 191 test_sys.iobridge.slave = test_sys.iobus.master 192 test_sys.iobridge.master = test_sys.membus.slave 193 194 # Sanity check 195 if options.fastmem: 196 if TestCPUClass != AtomicSimpleCPU: 197 fatal("Fastmem can only be used with atomic CPU!") 198 if (options.caches or options.l2cache): 199 fatal("You cannot use fastmem in combination with caches!") 200 201 if options.simpoint_profile: 202 if not options.fastmem: 203 # Atomic CPU checked with fastmem option already 204 fatal("SimPoint generation should be done with atomic cpu and fastmem") 205 if np > 1: 206 fatal("SimPoint generation not supported with more than one CPUs") 207 208 for i in xrange(np): 209 if options.fastmem: 210 test_sys.cpu[i].fastmem = True 211 if options.simpoint_profile: 212 test_sys.cpu[i].addSimPointProbe(options.simpoint_interval) 213 if options.checker: 214 test_sys.cpu[i].addCheckerCpu() 215 test_sys.cpu[i].createThreads() 216 217 # If elastic tracing is enabled when not restoring from checkpoint and 218 # when not fast forwarding using the atomic cpu, then check that the 219 # TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check 220 # passes then attach the elastic trace probe. 221 # If restoring from checkpoint or fast forwarding, the code that does this for 222 # FutureCPUClass is in the Simulation module. If the check passes then the 223 # elastic trace probe is attached to the switch CPUs. 224 if options.elastic_trace_en and options.checkpoint_restore == None and \ 225 not options.fast_forward: 226 CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options) 227 228 CacheConfig.config_cache(options, test_sys) 229 230 MemConfig.config_mem(options, test_sys) 231 232 return test_sys 233 234def build_drive_system(np): 235 # driver system CPU is always simple, so is the memory 236 # Note this is an assignment of a class, not an instance. 237 DriveCPUClass = AtomicSimpleCPU 238 drive_mem_mode = 'atomic' 239 DriveMemClass = SimpleMemory 240 241 cmdline = cmd_line_template() 242 if buildEnv['TARGET_ISA'] == 'alpha': 243 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1], cmdline=cmdline) 244 elif buildEnv['TARGET_ISA'] == 'mips': 245 drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1], cmdline=cmdline) 246 elif buildEnv['TARGET_ISA'] == 'sparc': 247 drive_sys = makeSparcSystem(drive_mem_mode, bm[1], cmdline=cmdline) 248 elif buildEnv['TARGET_ISA'] == 'x86': 249 drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1], 250 cmdline=cmdline) 251 elif buildEnv['TARGET_ISA'] == 'arm': 252 drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, np, 253 bm[1], options.dtb_filename, cmdline=cmdline) 254 255 # Create a top-level voltage domain 256 drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 257 258 # Create a source clock for the system and set the clock period 259 drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, 260 voltage_domain = drive_sys.voltage_domain) 261 262 # Create a CPU voltage domain 263 drive_sys.cpu_voltage_domain = VoltageDomain() 264 265 # Create a source clock for the CPUs and set the clock period 266 drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 267 voltage_domain = 268 drive_sys.cpu_voltage_domain) 269 270 drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain, 271 cpu_id=0) 272 drive_sys.cpu.createThreads() 273 drive_sys.cpu.createInterruptController() 274 drive_sys.cpu.connectAllPorts(drive_sys.membus) 275 if options.fastmem: 276 drive_sys.cpu.fastmem = True 277 if options.kernel is not None: 278 drive_sys.kernel = binary(options.kernel) 279 280 if is_kvm_cpu(DriveCPUClass): 281 drive_sys.vm = KvmVM() 282 283 drive_sys.iobridge = Bridge(delay='50ns', 284 ranges = drive_sys.mem_ranges) 285 drive_sys.iobridge.slave = drive_sys.iobus.master 286 drive_sys.iobridge.master = drive_sys.membus.slave 287 288 # Create the appropriate memory controllers and connect them to the 289 # memory bus 290 drive_sys.mem_ctrls = [DriveMemClass(range = r) 291 for r in drive_sys.mem_ranges] 292 for i in xrange(len(drive_sys.mem_ctrls)): 293 drive_sys.mem_ctrls[i].port = drive_sys.membus.master 294 295 drive_sys.init_param = options.init_param 296 297 return drive_sys 298 299# Add options 300parser = optparse.OptionParser() 301Options.addCommonOptions(parser) 302Options.addFSOptions(parser) 303 304# Add the ruby specific and protocol specific options 305if '--ruby' in sys.argv: 306 Ruby.define_options(parser) 307 308(options, args) = parser.parse_args() 309 310if args: 311 print "Error: script doesn't take any positional arguments" 312 sys.exit(1) 313 314# system under test can be any CPU 315(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 316 317# Match the memories with the CPUs, based on the options for the test system 318TestMemClass = Simulation.setMemClass(options) 319 320if options.benchmark: 321 try: 322 bm = Benchmarks[options.benchmark] 323 except KeyError: 324 print "Error benchmark %s has not been defined." % options.benchmark 325 print "Valid benchmarks are: %s" % DefinedBenchmarks 326 sys.exit(1) 327else: 328 if options.dual: 329 bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device, 330 mem=options.mem_size, os_type=options.os_type), 331 SysConfig(disk=options.disk_image, rootdev=options.root_device, 332 mem=options.mem_size, os_type=options.os_type)] 333 else: 334 bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device, 335 mem=options.mem_size, os_type=options.os_type)] 336 337np = options.num_cpus 338 339test_sys = build_test_system(np) 340if len(bm) == 2: 341 drive_sys = build_drive_system(np) 342 root = makeDualRoot(True, test_sys, drive_sys, options.etherdump) 343elif len(bm) == 1 and options.dist: 344 # This system is part of a dist-gem5 simulation 345 root = makeDistRoot(test_sys, 346 options.dist_rank, 347 options.dist_size, 348 options.dist_server_name, 349 options.dist_server_port, 350 options.dist_sync_repeat, 351 options.dist_sync_start, 352 options.ethernet_linkspeed, 353 options.ethernet_linkdelay, 354 options.etherdump); 355elif len(bm) == 1: 356 root = Root(full_system=True, system=test_sys) 357else: 358 print "Error I don't know how to create more than 2 systems." 359 sys.exit(1) 360 361if options.timesync: 362 root.time_sync_enable = True 363 364if options.frame_capture: 365 VncServer.frame_capture = True 366 367Simulation.setWorkCountOptions(test_sys, options) 368Simulation.run(options, root, test_sys, FutureClass) 369