fs.py revision 10119
15353Svilas.sridharan@gmail.com# Copyright (c) 2010-2013 ARM Limited 23395Shsul@eecs.umich.edu# All rights reserved. 33395Shsul@eecs.umich.edu# 43395Shsul@eecs.umich.edu# The license below extends only to copyright in the software and shall 53395Shsul@eecs.umich.edu# not be construed as granting a license to any other intellectual 63395Shsul@eecs.umich.edu# property including but not limited to intellectual property relating 73395Shsul@eecs.umich.edu# to a hardware implementation of the functionality of the software 83395Shsul@eecs.umich.edu# licensed hereunder. You may use the software subject to the license 93395Shsul@eecs.umich.edu# terms below provided that you ensure that this notice is replicated 103395Shsul@eecs.umich.edu# unmodified and in its entirety in all distributions of the software, 113395Shsul@eecs.umich.edu# modified or unmodified, in source code or in binary form. 123395Shsul@eecs.umich.edu# 133395Shsul@eecs.umich.edu# Copyright (c) 2012-2014 Mark D. Hill and David A. Wood 143395Shsul@eecs.umich.edu# Copyright (c) 2009-2011 Advanced Micro Devices, Inc. 153395Shsul@eecs.umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 163395Shsul@eecs.umich.edu# All rights reserved. 173395Shsul@eecs.umich.edu# 183395Shsul@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 193395Shsul@eecs.umich.edu# modification, are permitted provided that the following conditions are 203395Shsul@eecs.umich.edu# met: redistributions of source code must retain the above copyright 213395Shsul@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 223395Shsul@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 233395Shsul@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 243395Shsul@eecs.umich.edu# documentation and/or other materials provided with the distribution; 253395Shsul@eecs.umich.edu# neither the name of the copyright holders nor the names of its 263395Shsul@eecs.umich.edu# contributors may be used to endorse or promote products derived from 273395Shsul@eecs.umich.edu# this software without specific prior written permission. 283395Shsul@eecs.umich.edu# 298920Snilay@cs.wisc.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 308920Snilay@cs.wisc.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 318920Snilay@cs.wisc.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 328920Snilay@cs.wisc.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 337025SBrad.Beckmann@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 349520SAndreas.Sandberg@ARM.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 359520SAndreas.Sandberg@ARM.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 369520SAndreas.Sandberg@ARM.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 379520SAndreas.Sandberg@ARM.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 389520SAndreas.Sandberg@ARM.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 399520SAndreas.Sandberg@ARM.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 408920Snilay@cs.wisc.edu# 418920Snilay@cs.wisc.edu# Authors: Ali Saidi 429520SAndreas.Sandberg@ARM.com# Brad Beckmann 439520SAndreas.Sandberg@ARM.com 449520SAndreas.Sandberg@ARM.comimport optparse 458920Snilay@cs.wisc.eduimport sys 469520SAndreas.Sandberg@ARM.com 478920Snilay@cs.wisc.eduimport m5 488920Snilay@cs.wisc.edufrom m5.defines import buildEnv 498920Snilay@cs.wisc.edufrom m5.objects import * 508920Snilay@cs.wisc.edufrom m5.util import addToPath, fatal 518920Snilay@cs.wisc.edu 528920Snilay@cs.wisc.eduaddToPath('../common') 538920Snilay@cs.wisc.eduaddToPath('../ruby') 548920Snilay@cs.wisc.edu 558920Snilay@cs.wisc.eduimport Ruby 568920Snilay@cs.wisc.edu 578920Snilay@cs.wisc.edufrom FSConfig import * 588920Snilay@cs.wisc.edufrom SysPaths import * 598920Snilay@cs.wisc.edufrom Benchmarks import * 608920Snilay@cs.wisc.eduimport Simulation 618920Snilay@cs.wisc.eduimport CacheConfig 628920Snilay@cs.wisc.eduimport MemConfig 638920Snilay@cs.wisc.edufrom Caches import * 648920Snilay@cs.wisc.eduimport Options 658920Snilay@cs.wisc.edu 668920Snilay@cs.wisc.edu 679197Snilay@cs.wisc.edu# Check if KVM support has been enabled, we might need to do VM 689197Snilay@cs.wisc.edu# configuration if that's the case. 699197Snilay@cs.wisc.eduhave_kvm_support = 'BaseKvmCPU' in globals() 709197Snilay@cs.wisc.edudef is_kvm_cpu(cpu_class): 719197Snilay@cs.wisc.edu return have_kvm_support and cpu_class != None and \ 723395Shsul@eecs.umich.edu issubclass(cpu_class, BaseKvmCPU) 738920Snilay@cs.wisc.edu 748920Snilay@cs.wisc.edudef build_test_system(np): 758920Snilay@cs.wisc.edu if buildEnv['TARGET_ISA'] == "alpha": 768920Snilay@cs.wisc.edu test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby) 778920Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == "mips": 788920Snilay@cs.wisc.edu test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0]) 798920Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == "sparc": 808920Snilay@cs.wisc.edu test_sys = makeSparcSystem(test_mem_mode, bm[0]) 818920Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == "x86": 828920Snilay@cs.wisc.edu test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0], 838920Snilay@cs.wisc.edu options.ruby) 848920Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == "arm": 858920Snilay@cs.wisc.edu test_sys = makeArmSystem(test_mem_mode, options.machine_type, bm[0], 868920Snilay@cs.wisc.edu options.dtb_filename, 878920Snilay@cs.wisc.edu bare_metal=options.bare_metal) 888920Snilay@cs.wisc.edu if options.enable_context_switch_stats_dump: 898920Snilay@cs.wisc.edu test_sys.enable_context_switch_stats_dump = True 908920Snilay@cs.wisc.edu else: 916776SBrad.Beckmann@amd.com fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) 928920Snilay@cs.wisc.edu 938920Snilay@cs.wisc.edu # Set the cache line size for the entire system 948920Snilay@cs.wisc.edu test_sys.cache_line_size = options.cacheline_size 958920Snilay@cs.wisc.edu 969357Sandreas.hansson@arm.com # Create a top-level voltage domain 978920Snilay@cs.wisc.edu test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 988920Snilay@cs.wisc.edu 998920Snilay@cs.wisc.edu # Create a source clock for the system and set the clock period 1008920Snilay@cs.wisc.edu test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, 1018920Snilay@cs.wisc.edu voltage_domain = test_sys.voltage_domain) 1028920Snilay@cs.wisc.edu 1038920Snilay@cs.wisc.edu # Create a CPU voltage domain 1048920Snilay@cs.wisc.edu test_sys.cpu_voltage_domain = VoltageDomain() 1058920Snilay@cs.wisc.edu 1068920Snilay@cs.wisc.edu # Create a source clock for the CPUs and set the clock period 1078920Snilay@cs.wisc.edu test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 1088920Snilay@cs.wisc.edu voltage_domain = 1098920Snilay@cs.wisc.edu test_sys.cpu_voltage_domain) 1108920Snilay@cs.wisc.edu 1118920Snilay@cs.wisc.edu if options.kernel is not None: 1128920Snilay@cs.wisc.edu test_sys.kernel = binary(options.kernel) 1138920Snilay@cs.wisc.edu 1148920Snilay@cs.wisc.edu if options.script is not None: 1153395Shsul@eecs.umich.edu test_sys.readfile = options.script 1165361Srstrong@cs.ucsd.edu 1178920Snilay@cs.wisc.edu if options.lpae: 1188920Snilay@cs.wisc.edu test_sys.have_lpae = True 1198920Snilay@cs.wisc.edu 1209151Satgutier@umich.edu if options.virtualisation: 1219151Satgutier@umich.edu test_sys.have_virtualization = True 1229151Satgutier@umich.edu 1239151Satgutier@umich.edu test_sys.init_param = options.init_param 1249151Satgutier@umich.edu 1259151Satgutier@umich.edu # For now, assign all the CPUs to the same clock domain 1269562Ssaidi@eecs.umich.edu test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) 1278920Snilay@cs.wisc.edu for i in xrange(np)] 1288920Snilay@cs.wisc.edu 1298920Snilay@cs.wisc.edu if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass): 1308920Snilay@cs.wisc.edu test_sys.vm = KvmVM() 1318920Snilay@cs.wisc.edu 1328920Snilay@cs.wisc.edu if options.ruby: 1338920Snilay@cs.wisc.edu # Check for timing mode because ruby does not support atomic accesses 1348920Snilay@cs.wisc.edu if not (options.cpu_type == "detailed" or options.cpu_type == "timing"): 1358920Snilay@cs.wisc.edu print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!" 1368920Snilay@cs.wisc.edu sys.exit(1) 1378920Snilay@cs.wisc.edu 1388920Snilay@cs.wisc.edu Ruby.create_system(options, test_sys, test_sys.iobus, test_sys._dma_ports) 1398920Snilay@cs.wisc.edu 1408920Snilay@cs.wisc.edu # Create a seperate clock domain for Ruby 1418920Snilay@cs.wisc.edu test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 1428920Snilay@cs.wisc.edu voltage_domain = test_sys.voltage_domain) 1438920Snilay@cs.wisc.edu 1448920Snilay@cs.wisc.edu for (i, cpu) in enumerate(test_sys.cpu): 1458920Snilay@cs.wisc.edu # 1468920Snilay@cs.wisc.edu # Tie the cpu ports to the correct ruby system ports 1478920Snilay@cs.wisc.edu # 1488920Snilay@cs.wisc.edu cpu.clk_domain = test_sys.cpu_clk_domain 1498920Snilay@cs.wisc.edu cpu.createThreads() 1508920Snilay@cs.wisc.edu cpu.createInterruptController() 1518920Snilay@cs.wisc.edu 1528920Snilay@cs.wisc.edu cpu.icache_port = test_sys.ruby._cpu_ruby_ports[i].slave 1538920Snilay@cs.wisc.edu cpu.dcache_port = test_sys.ruby._cpu_ruby_ports[i].slave 1548920Snilay@cs.wisc.edu 1558920Snilay@cs.wisc.edu if buildEnv['TARGET_ISA'] == "x86": 1568920Snilay@cs.wisc.edu cpu.itb.walker.port = test_sys.ruby._cpu_ruby_ports[i].slave 1578920Snilay@cs.wisc.edu cpu.dtb.walker.port = test_sys.ruby._cpu_ruby_ports[i].slave 1588920Snilay@cs.wisc.edu 1598920Snilay@cs.wisc.edu cpu.interrupts.pio = test_sys.ruby._cpu_ruby_ports[i].master 1608920Snilay@cs.wisc.edu cpu.interrupts.int_master = test_sys.ruby._cpu_ruby_ports[i].slave 1618920Snilay@cs.wisc.edu cpu.interrupts.int_slave = test_sys.ruby._cpu_ruby_ports[i].master 1628920Snilay@cs.wisc.edu 1638920Snilay@cs.wisc.edu test_sys.ruby._cpu_ruby_ports[i].access_phys_mem = True 1648920Snilay@cs.wisc.edu 1658920Snilay@cs.wisc.edu # Create the appropriate memory controllers 1668920Snilay@cs.wisc.edu # and connect them to the IO bus 1678920Snilay@cs.wisc.edu test_sys.mem_ctrls = [TestMemClass(range = r) for r in test_sys.mem_ranges] 1688920Snilay@cs.wisc.edu for i in xrange(len(test_sys.mem_ctrls)): 1698920Snilay@cs.wisc.edu test_sys.mem_ctrls[i].port = test_sys.iobus.master 1708920Snilay@cs.wisc.edu 1718920Snilay@cs.wisc.edu else: 1728920Snilay@cs.wisc.edu if options.caches or options.l2cache: 1738920Snilay@cs.wisc.edu # By default the IOCache runs at the system clock 1748920Snilay@cs.wisc.edu test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges) 1758920Snilay@cs.wisc.edu test_sys.iocache.cpu_side = test_sys.iobus.master 1769539Satgutier@umich.edu test_sys.iocache.mem_side = test_sys.membus.slave 1779539Satgutier@umich.edu else: 1789539Satgutier@umich.edu test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) 1798920Snilay@cs.wisc.edu test_sys.iobridge.slave = test_sys.iobus.master 1808920Snilay@cs.wisc.edu test_sys.iobridge.master = test_sys.membus.slave 1818920Snilay@cs.wisc.edu 1828920Snilay@cs.wisc.edu # Sanity check 1838920Snilay@cs.wisc.edu if options.fastmem: 1848920Snilay@cs.wisc.edu if TestCPUClass != AtomicSimpleCPU: 1858920Snilay@cs.wisc.edu fatal("Fastmem can only be used with atomic CPU!") 1868920Snilay@cs.wisc.edu if (options.caches or options.l2cache): 1878920Snilay@cs.wisc.edu fatal("You cannot use fastmem in combination with caches!") 1888920Snilay@cs.wisc.edu 1898920Snilay@cs.wisc.edu for i in xrange(np): 1908920Snilay@cs.wisc.edu if options.fastmem: 1918956Sjayneel@cs.wisc.edu test_sys.cpu[i].fastmem = True 1928956Sjayneel@cs.wisc.edu if options.checker: 1938956Sjayneel@cs.wisc.edu test_sys.cpu[i].addCheckerCpu() 1948956Sjayneel@cs.wisc.edu test_sys.cpu[i].createThreads() 1958956Sjayneel@cs.wisc.edu 1968956Sjayneel@cs.wisc.edu CacheConfig.config_cache(options, test_sys) 1978956Sjayneel@cs.wisc.edu MemConfig.config_mem(options, test_sys) 1988976Sjayneel@cs.wisc.edu 199 return test_sys 200 201def build_drive_system(np): 202 # driver system CPU is always simple, so is the memory 203 # Note this is an assignment of a class, not an instance. 204 DriveCPUClass = AtomicSimpleCPU 205 drive_mem_mode = 'atomic' 206 DriveMemClass = SimpleMemory 207 208 if buildEnv['TARGET_ISA'] == 'alpha': 209 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1]) 210 elif buildEnv['TARGET_ISA'] == 'mips': 211 drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1]) 212 elif buildEnv['TARGET_ISA'] == 'sparc': 213 drive_sys = makeSparcSystem(drive_mem_mode, bm[1]) 214 elif buildEnv['TARGET_ISA'] == 'x86': 215 drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1]) 216 elif buildEnv['TARGET_ISA'] == 'arm': 217 drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1]) 218 219 # Create a top-level voltage domain 220 drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 221 222 # Create a source clock for the system and set the clock period 223 drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, 224 voltage_domain = drive_sys.voltage_domain) 225 226 # Create a CPU voltage domain 227 drive_sys.cpu_voltage_domain = VoltageDomain() 228 229 # Create a source clock for the CPUs and set the clock period 230 drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 231 voltage_domain = 232 drive_sys.cpu_voltage_domain) 233 234 drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain, 235 cpu_id=0) 236 drive_sys.cpu.createThreads() 237 drive_sys.cpu.createInterruptController() 238 drive_sys.cpu.connectAllPorts(drive_sys.membus) 239 if options.fastmem: 240 drive_sys.cpu.fastmem = True 241 if options.kernel is not None: 242 drive_sys.kernel = binary(options.kernel) 243 244 if is_kvm_cpu(DriveCPUClass): 245 drive_sys.vm = KvmVM() 246 247 drive_sys.iobridge = Bridge(delay='50ns', 248 ranges = drive_sys.mem_ranges) 249 drive_sys.iobridge.slave = drive_sys.iobus.master 250 drive_sys.iobridge.master = drive_sys.membus.slave 251 252 # Create the appropriate memory controllers and connect them to the 253 # memory bus 254 drive_sys.mem_ctrls = [DriveMemClass(range = r) 255 for r in drive_sys.mem_ranges] 256 for i in xrange(len(drive_sys.mem_ctrls)): 257 drive_sys.mem_ctrls[i].port = drive_sys.membus.master 258 259 drive_sys.init_param = options.init_param 260 261 return drive_sys 262 263# Add options 264parser = optparse.OptionParser() 265Options.addCommonOptions(parser) 266Options.addFSOptions(parser) 267 268# Add the ruby specific and protocol specific options 269if '--ruby' in sys.argv: 270 Ruby.define_options(parser) 271 272(options, args) = parser.parse_args() 273 274if args: 275 print "Error: script doesn't take any positional arguments" 276 sys.exit(1) 277 278# system under test can be any CPU 279(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 280 281# Match the memories with the CPUs, based on the options for the test system 282TestMemClass = Simulation.setMemClass(options) 283 284if options.benchmark: 285 try: 286 bm = Benchmarks[options.benchmark] 287 except KeyError: 288 print "Error benchmark %s has not been defined." % options.benchmark 289 print "Valid benchmarks are: %s" % DefinedBenchmarks 290 sys.exit(1) 291else: 292 if options.dual: 293 bm = [SysConfig(disk=options.disk_image, mem=options.mem_size), 294 SysConfig(disk=options.disk_image, mem=options.mem_size)] 295 else: 296 bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)] 297 298np = options.num_cpus 299 300test_sys = build_test_system(np) 301if len(bm) == 2: 302 drive_sys = build_drive_system(np) 303 root = makeDualRoot(True, test_sys, drive_sys, options.etherdump) 304elif len(bm) == 1: 305 root = Root(full_system=True, system=test_sys) 306else: 307 print "Error I don't know how to create more than 2 systems." 308 sys.exit(1) 309 310if options.timesync: 311 root.time_sync_enable = True 312 313if options.frame_capture: 314 VncServer.frame_capture = True 315 316Simulation.setWorkCountOptions(test_sys, options) 317Simulation.run(options, root, test_sys, FutureClass) 318