etrace_replay.py revision 13774
11689SN/A# Copyright (c) 2015 ARM Limited 214025Sgiacomo.gabrielli@arm.com# All rights reserved. 39920Syasuko.eckert@amd.com# 47944SGiacomo.Gabrielli@arm.com# The license below extends only to copyright in the software and shall 57944SGiacomo.Gabrielli@arm.com# not be construed as granting a license to any other intellectual 67944SGiacomo.Gabrielli@arm.com# property including but not limited to intellectual property relating 77944SGiacomo.Gabrielli@arm.com# to a hardware implementation of the functionality of the software 87944SGiacomo.Gabrielli@arm.com# licensed hereunder. You may use the software subject to the license 97944SGiacomo.Gabrielli@arm.com# terms below provided that you ensure that this notice is replicated 107944SGiacomo.Gabrielli@arm.com# unmodified and in its entirety in all distributions of the software, 117944SGiacomo.Gabrielli@arm.com# modified or unmodified, in source code or in binary form. 127944SGiacomo.Gabrielli@arm.com# 137944SGiacomo.Gabrielli@arm.com# Redistribution and use in source and binary forms, with or without 147944SGiacomo.Gabrielli@arm.com# modification, are permitted provided that the following conditions are 152326SN/A# met: redistributions of source code must retain the above copyright 161689SN/A# notice, this list of conditions and the following disclaimer; 171689SN/A# redistributions in binary form must reproduce the above copyright 181689SN/A# notice, this list of conditions and the following disclaimer in the 191689SN/A# documentation and/or other materials provided with the distribution; 201689SN/A# neither the name of the copyright holders nor the names of its 211689SN/A# contributors may be used to endorse or promote products derived from 221689SN/A# this software without specific prior written permission. 231689SN/A# 241689SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 251689SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 261689SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 271689SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 281689SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 291689SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 301689SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 311689SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 321689SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 331689SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 341689SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 351689SN/A# 361689SN/A# Authors: Radhika Jagtap 371689SN/A 381689SN/A# Basic elastic traces replay script that configures a Trace CPU 391689SN/A 402665Ssaidi@eecs.umich.edufrom __future__ import print_function 412665Ssaidi@eecs.umich.edufrom __future__ import absolute_import 422831Sksewell@umich.edu 431689SN/Aimport optparse 441689SN/A 459944Smatt.horsnell@ARM.comfrom m5.util import addToPath, fatal 469944Smatt.horsnell@ARM.com 479944Smatt.horsnell@ARM.comaddToPath('../') 482064SN/A 491060SN/Afrom common import Options 501060SN/Afrom common import Simulation 5113449Sgabeblack@google.comfrom common import CacheConfig 522292SN/Afrom common import MemConfig 531717SN/Afrom common.Caches import * 548232Snate@binkert.org 554762Snate@binkert.orgparser = optparse.OptionParser() 566221Snate@binkert.orgOptions.addCommonOptions(parser) 574762Snate@binkert.org 581060SN/Aif '--ruby' in sys.argv: 598737Skoansin.tan@gmail.com print("This script does not support Ruby configuration, mainly" 608737Skoansin.tan@gmail.com " because Trace CPU has been tested only with classic memory system") 618737Skoansin.tan@gmail.com sys.exit(1) 625529Snate@binkert.org 631061SN/A(options, args) = parser.parse_args() 6413429Srekai.gonzalezalberquilla@arm.com 655606Snate@binkert.orgif args: 668581Ssteve.reinhardt@amd.com print("Error: script doesn't take any positional arguments") 678581Ssteve.reinhardt@amd.com sys.exit(1) 681060SN/A 692292SN/AnumThreads = 1 702292SN/A 712292SN/Aif options.cpu_type != "TraceCPU": 722292SN/A fatal("This is a script for elastic trace replay simulation, use "\ 732292SN/A "--cpu-type=TraceCPU\n"); 742292SN/A 752326SN/Aif options.num_cpus > 1: 762292SN/A fatal("This script does not support multi-processor trace replay.\n") 772292SN/A 782292SN/A# In this case FutureClass will be None as there is not fast forwarding or 792292SN/A# switching 802292SN/A(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 812292SN/ACPUClass.numThreads = numThreads 825336Shines@cs.fsu.edu 832292SN/Asystem = System(cpu = CPUClass(cpu_id=0), 844873Sstever@eecs.umich.edu mem_mode = test_mem_mode, 852292SN/A mem_ranges = [AddrRange(options.mem_size)], 862292SN/A cache_line_size = options.cacheline_size) 872292SN/A 884329Sktlim@umich.edu# Create a top-level voltage domain 895529Snate@binkert.orgsystem.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 904329Sktlim@umich.edu 914329Sktlim@umich.edu# Create a source clock for the system. This is used as the clock period for 924329Sktlim@umich.edu# xbar and memory 9313561Snikos.nikoleris@arm.comsystem.clk_domain = SrcClockDomain(clock = options.sys_clock, 942292SN/A voltage_domain = system.voltage_domain) 952292SN/A 962292SN/A# Create a CPU voltage domain 972292SN/Asystem.cpu_voltage_domain = VoltageDomain() 982292SN/A 992292SN/A# Create a separate clock domain for the CPUs. In case of Trace CPUs this clock 1005529Snate@binkert.org# is actually used only by the caches connected to the CPU. 1011060SN/Asystem.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 1029920Syasuko.eckert@amd.com voltage_domain = 10312109SRekai.GonzalezAlberquilla@arm.com system.cpu_voltage_domain) 1049920Syasuko.eckert@amd.com 10512109SRekai.GonzalezAlberquilla@arm.com# All cpus belong to a common cpu_clk_domain, therefore running at a common 10612109SRekai.GonzalezAlberquilla@arm.com# frequency. 10713610Sgiacomo.gabrielli@arm.comfor cpu in system.cpu: 10812109SRekai.GonzalezAlberquilla@arm.com cpu.clk_domain = system.cpu_clk_domain 1091060SN/A 1101060SN/A# BaseCPU no longer has default values for the BaseCPU.isa 1111060SN/A# createThreads() is needed to fill in the cpu.isa 1122326SN/Afor cpu in system.cpu: 1131060SN/A cpu.createThreads() 1141060SN/A 1151060SN/A# Assign input trace files to the Trace CPU 1161060SN/Asystem.cpu.instTraceFile=options.inst_trace_file 1172292SN/Asystem.cpu.dataTraceFile=options.data_trace_file 11813453Srekai.gonzalezalberquilla@arm.com 1196221Snate@binkert.org# Configure the classic memory system options 1206221Snate@binkert.orgMemClass = Simulation.setMemClass(options) 1211060SN/Asystem.membus = SystemXBar() 1221060SN/Asystem.system_port = system.membus.slave 1232307SN/ACacheConfig.config_cache(options, system) 1242292SN/AMemConfig.config_mem(options, system) 1252292SN/A 12613561Snikos.nikoleris@arm.comroot = Root(full_system = False, system = system) 1272292SN/ASimulation.run(options, root, system, FutureClass) 1286221Snate@binkert.org