etrace_replay.py revision 13774
19243SN/A# Copyright (c) 2015 ARM Limited 212705Swendy.elsasser@arm.com# All rights reserved. 39243SN/A# 49243SN/A# The license below extends only to copyright in the software and shall 59243SN/A# not be construed as granting a license to any other intellectual 69243SN/A# property including but not limited to intellectual property relating 79243SN/A# to a hardware implementation of the functionality of the software 89243SN/A# licensed hereunder. You may use the software subject to the license 99243SN/A# terms below provided that you ensure that this notice is replicated 109243SN/A# unmodified and in its entirety in all distributions of the software, 119243SN/A# modified or unmodified, in source code or in binary form. 129243SN/A# 139243SN/A# Redistribution and use in source and binary forms, with or without 149831SN/A# modification, are permitted provided that the following conditions are 159831SN/A# met: redistributions of source code must retain the above copyright 169831SN/A# notice, this list of conditions and the following disclaimer; 179243SN/A# redistributions in binary form must reproduce the above copyright 189243SN/A# notice, this list of conditions and the following disclaimer in the 199243SN/A# documentation and/or other materials provided with the distribution; 209243SN/A# neither the name of the copyright holders nor the names of its 219243SN/A# contributors may be used to endorse or promote products derived from 229243SN/A# this software without specific prior written permission. 239243SN/A# 249243SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 259243SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 269243SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 279243SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 289243SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 299243SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 309243SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 319243SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 329243SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 339243SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 349243SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 359243SN/A# 369243SN/A# Authors: Radhika Jagtap 379243SN/A 389243SN/A# Basic elastic traces replay script that configures a Trace CPU 399243SN/A 409243SN/Afrom __future__ import print_function 419243SN/Afrom __future__ import absolute_import 429967SN/A 4310618SOmar.Naji@arm.comimport optparse 4411555Sjungma@eit.uni-kl.de 4511678Swendy.elsasser@arm.comfrom m5.util import addToPath, fatal 4612266Sradhika.jagtap@arm.com 479243SN/AaddToPath('../') 489243SN/A 499243SN/Afrom common import Options 509243SN/Afrom common import Simulation 5110146Sandreas.hansson@arm.comfrom common import CacheConfig 529243SN/Afrom common import MemConfig 539243SN/Afrom common.Caches import * 5410146Sandreas.hansson@arm.com 5510146Sandreas.hansson@arm.comparser = optparse.OptionParser() 569243SN/AOptions.addCommonOptions(parser) 579488SN/A 5810618SOmar.Naji@arm.comif '--ruby' in sys.argv: 5910889Sandreas.hansson@arm.com print("This script does not support Ruby configuration, mainly" 609488SN/A " because Trace CPU has been tested only with classic memory system") 6111677Swendy.elsasser@arm.com sys.exit(1) 629243SN/A 639243SN/A(options, args) = parser.parse_args() 649243SN/A 659243SN/Aif args: 669243SN/A print("Error: script doesn't take any positional arguments") 679243SN/A sys.exit(1) 6810146Sandreas.hansson@arm.com 699243SN/AnumThreads = 1 7010432SOmar.Naji@arm.com 719243SN/Aif options.cpu_type != "TraceCPU": 729243SN/A fatal("This is a script for elastic trace replay simulation, use "\ 7310287Sandreas.hansson@arm.com "--cpu-type=TraceCPU\n"); 7410287Sandreas.hansson@arm.com 7510287Sandreas.hansson@arm.comif options.num_cpus > 1: 7610287Sandreas.hansson@arm.com fatal("This script does not support multi-processor trace replay.\n") 7710287Sandreas.hansson@arm.com 789243SN/A# In this case FutureClass will be None as there is not fast forwarding or 7910287Sandreas.hansson@arm.com# switching 8010287Sandreas.hansson@arm.com(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 8110287Sandreas.hansson@arm.comCPUClass.numThreads = numThreads 8210287Sandreas.hansson@arm.com 8310287Sandreas.hansson@arm.comsystem = System(cpu = CPUClass(cpu_id=0), 8410287Sandreas.hansson@arm.com mem_mode = test_mem_mode, 8510287Sandreas.hansson@arm.com mem_ranges = [AddrRange(options.mem_size)], 8610287Sandreas.hansson@arm.com cache_line_size = options.cacheline_size) 8710287Sandreas.hansson@arm.com 8810287Sandreas.hansson@arm.com# Create a top-level voltage domain 8910287Sandreas.hansson@arm.comsystem.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 9010287Sandreas.hansson@arm.com 9110287Sandreas.hansson@arm.com# Create a source clock for the system. This is used as the clock period for 9211678Swendy.elsasser@arm.com# xbar and memory 9311678Swendy.elsasser@arm.comsystem.clk_domain = SrcClockDomain(clock = options.sys_clock, 9411678Swendy.elsasser@arm.com voltage_domain = system.voltage_domain) 9511678Swendy.elsasser@arm.com 969243SN/A# Create a CPU voltage domain 9710146Sandreas.hansson@arm.comsystem.cpu_voltage_domain = VoltageDomain() 989243SN/A 999243SN/A# Create a separate clock domain for the CPUs. In case of Trace CPUs this clock 1009243SN/A# is actually used only by the caches connected to the CPU. 1019243SN/Asystem.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 1029243SN/A voltage_domain = 1039243SN/A system.cpu_voltage_domain) 1049243SN/A 1059243SN/A# All cpus belong to a common cpu_clk_domain, therefore running at a common 1069243SN/A# frequency. 10710713Sandreas.hansson@arm.comfor cpu in system.cpu: 10810146Sandreas.hansson@arm.com cpu.clk_domain = system.cpu_clk_domain 1099243SN/A 1109243SN/A# BaseCPU no longer has default values for the BaseCPU.isa 1119243SN/A# createThreads() is needed to fill in the cpu.isa 11210146Sandreas.hansson@arm.comfor cpu in system.cpu: 1139243SN/A cpu.createThreads() 1149243SN/A 1159243SN/A# Assign input trace files to the Trace CPU 1169243SN/Asystem.cpu.instTraceFile=options.inst_trace_file 1179243SN/Asystem.cpu.dataTraceFile=options.data_trace_file 1189243SN/A 1199243SN/A# Configure the classic memory system options 1209243SN/AMemClass = Simulation.setMemClass(options) 1219243SN/Asystem.membus = SystemXBar() 1229243SN/Asystem.system_port = system.membus.slave 1239243SN/ACacheConfig.config_cache(options, system) 1249243SN/AMemConfig.config_mem(options, system) 1259243SN/A 1269243SN/Aroot = Root(full_system = False, system = system) 1279243SN/ASimulation.run(options, root, system, FutureClass) 1289243SN/A