etrace_replay.py revision 13774 
1# Copyright (c) 2015 ARM Limited
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35#
36# Authors: Radhika Jagtap
37
38# Basic elastic traces replay script that configures a Trace CPU
39
40from __future__ import print_function
41from __future__ import absolute_import
42
43import optparse
44
45from m5.util import addToPath, fatal
46
47addToPath('../')
48
49from common import Options
50from common import Simulation
51from common import CacheConfig
52from common import MemConfig
53from common.Caches import *
54
55parser = optparse.OptionParser()
56Options.addCommonOptions(parser)
57
58if '--ruby' in sys.argv:
59    print("This script does not support Ruby configuration, mainly"
60    " because Trace CPU has been tested only with classic memory system")
61    sys.exit(1)
62
63(options, args) = parser.parse_args()
64
65if args:
66    print("Error: script doesn't take any positional arguments")
67    sys.exit(1)
68
69numThreads = 1
70
71if options.cpu_type != "TraceCPU":
72    fatal("This is a script for elastic trace replay simulation, use "\
73            "--cpu-type=TraceCPU\n");
74
75if options.num_cpus > 1:
76    fatal("This script does not support multi-processor trace replay.\n")
77
78# In this case FutureClass will be None as there is not fast forwarding or
79# switching
80(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
81CPUClass.numThreads = numThreads
82
83system = System(cpu = CPUClass(cpu_id=0),
84                mem_mode = test_mem_mode,
85                mem_ranges = [AddrRange(options.mem_size)],
86                cache_line_size = options.cacheline_size)
87
88# Create a top-level voltage domain
89system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
90
91# Create a source clock for the system. This is used as the clock period for
92# xbar and memory
93system.clk_domain = SrcClockDomain(clock =  options.sys_clock,
94                                   voltage_domain = system.voltage_domain)
95
96# Create a CPU voltage domain
97system.cpu_voltage_domain = VoltageDomain()
98
99# Create a separate clock domain for the CPUs. In case of Trace CPUs this clock
100# is actually used only by the caches connected to the CPU.
101system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
102                                       voltage_domain =
103                                       system.cpu_voltage_domain)
104
105# All cpus belong to a common cpu_clk_domain, therefore running at a common
106# frequency.
107for cpu in system.cpu:
108    cpu.clk_domain = system.cpu_clk_domain
109
110# BaseCPU no longer has default values for the BaseCPU.isa
111# createThreads() is needed to fill in the cpu.isa
112for cpu in system.cpu:
113    cpu.createThreads()
114
115# Assign input trace files to the Trace CPU
116system.cpu.instTraceFile=options.inst_trace_file
117system.cpu.dataTraceFile=options.data_trace_file
118
119# Configure the classic memory system options
120MemClass = Simulation.setMemClass(options)
121system.membus = SystemXBar()
122system.system_port = system.membus.slave
123CacheConfig.config_cache(options, system)
124MemConfig.config_mem(options, system)
125
126root = Root(full_system = False, system = system)
127Simulation.run(options, root, system, FutureClass)
128