etrace_replay.py revision 12564
14876Sstever@eecs.umich.edu# Copyright (c) 2015 ARM Limited 23646Srdreslin@umich.edu# All rights reserved. 33646Srdreslin@umich.edu# 43646Srdreslin@umich.edu# The license below extends only to copyright in the software and shall 53646Srdreslin@umich.edu# not be construed as granting a license to any other intellectual 63646Srdreslin@umich.edu# property including but not limited to intellectual property relating 73646Srdreslin@umich.edu# to a hardware implementation of the functionality of the software 83646Srdreslin@umich.edu# licensed hereunder. You may use the software subject to the license 93646Srdreslin@umich.edu# terms below provided that you ensure that this notice is replicated 103646Srdreslin@umich.edu# unmodified and in its entirety in all distributions of the software, 113646Srdreslin@umich.edu# modified or unmodified, in source code or in binary form. 123646Srdreslin@umich.edu# 133646Srdreslin@umich.edu# Redistribution and use in source and binary forms, with or without 143646Srdreslin@umich.edu# modification, are permitted provided that the following conditions are 153646Srdreslin@umich.edu# met: redistributions of source code must retain the above copyright 163646Srdreslin@umich.edu# notice, this list of conditions and the following disclaimer; 173646Srdreslin@umich.edu# redistributions in binary form must reproduce the above copyright 183646Srdreslin@umich.edu# notice, this list of conditions and the following disclaimer in the 193646Srdreslin@umich.edu# documentation and/or other materials provided with the distribution; 203646Srdreslin@umich.edu# neither the name of the copyright holders nor the names of its 213646Srdreslin@umich.edu# contributors may be used to endorse or promote products derived from 223646Srdreslin@umich.edu# this software without specific prior written permission. 233646Srdreslin@umich.edu# 243646Srdreslin@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 253646Srdreslin@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 263646Srdreslin@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 273646Srdreslin@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 283646Srdreslin@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 293646Srdreslin@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 303646Srdreslin@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 313646Srdreslin@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 323646Srdreslin@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 336654Snate@binkert.org# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 346654Snate@binkert.org# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 356654Snate@binkert.org# 366654Snate@binkert.org# Authors: Radhika Jagtap 373646Srdreslin@umich.edu 383646Srdreslin@umich.edu# Basic elastic traces replay script that configures a Trace CPU 396654Snate@binkert.org 406654Snate@binkert.orgfrom __future__ import print_function 413646Srdreslin@umich.edu 423646Srdreslin@umich.eduimport optparse 433646Srdreslin@umich.edu 443646Srdreslin@umich.edufrom m5.util import addToPath, fatal 453646Srdreslin@umich.edu 463646Srdreslin@umich.eduaddToPath('../') 473646Srdreslin@umich.edu 483646Srdreslin@umich.edufrom common import Options 493646Srdreslin@umich.edufrom common import Simulation 503646Srdreslin@umich.edufrom common import CacheConfig 513646Srdreslin@umich.edufrom common import MemConfig 523646Srdreslin@umich.edufrom common.Caches import * 533646Srdreslin@umich.edu 543646Srdreslin@umich.eduparser = optparse.OptionParser() 553646Srdreslin@umich.eduOptions.addCommonOptions(parser) 563646Srdreslin@umich.edu 573646Srdreslin@umich.eduif '--ruby' in sys.argv: 583646Srdreslin@umich.edu print("This script does not support Ruby configuration, mainly" 593646Srdreslin@umich.edu " because Trace CPU has been tested only with classic memory system") 603646Srdreslin@umich.edu sys.exit(1) 613646Srdreslin@umich.edu 623646Srdreslin@umich.edu(options, args) = parser.parse_args() 633646Srdreslin@umich.edu 643646Srdreslin@umich.eduif args: 653646Srdreslin@umich.edu print("Error: script doesn't take any positional arguments") 663646Srdreslin@umich.edu sys.exit(1) 673646Srdreslin@umich.edu 683646Srdreslin@umich.edunumThreads = 1 693646Srdreslin@umich.edu 703646Srdreslin@umich.eduif options.cpu_type != "TraceCPU": 713646Srdreslin@umich.edu fatal("This is a script for elastic trace replay simulation, use "\ 723646Srdreslin@umich.edu "--cpu-type=TraceCPU\n"); 733646Srdreslin@umich.edu 743646Srdreslin@umich.eduif options.num_cpus > 1: 753646Srdreslin@umich.edu fatal("This script does not support multi-processor trace replay.\n") 763646Srdreslin@umich.edu 773646Srdreslin@umich.edu# In this case FutureClass will be None as there is not fast forwarding or 783646Srdreslin@umich.edu# switching 793646Srdreslin@umich.edu(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 803646Srdreslin@umich.eduCPUClass.numThreads = numThreads 813646Srdreslin@umich.edu 823646Srdreslin@umich.edusystem = System(cpu = CPUClass(cpu_id=0), 833646Srdreslin@umich.edu mem_mode = test_mem_mode, 843646Srdreslin@umich.edu mem_ranges = [AddrRange(options.mem_size)], 853646Srdreslin@umich.edu cache_line_size = options.cacheline_size) 863646Srdreslin@umich.edu 873646Srdreslin@umich.edu# Create a top-level voltage domain 883646Srdreslin@umich.edusystem.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 893646Srdreslin@umich.edu 903646Srdreslin@umich.edu# Create a source clock for the system. This is used as the clock period for 913646Srdreslin@umich.edu# xbar and memory 923646Srdreslin@umich.edusystem.clk_domain = SrcClockDomain(clock = options.sys_clock, 933646Srdreslin@umich.edu voltage_domain = system.voltage_domain) 943646Srdreslin@umich.edu 953646Srdreslin@umich.edu# Create a CPU voltage domain 963646Srdreslin@umich.edusystem.cpu_voltage_domain = VoltageDomain() 973646Srdreslin@umich.edu 983646Srdreslin@umich.edu# Create a separate clock domain for the CPUs. In case of Trace CPUs this clock 993646Srdreslin@umich.edu# is actually used only by the caches connected to the CPU. 1003646Srdreslin@umich.edusystem.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 1013646Srdreslin@umich.edu voltage_domain = 1023646Srdreslin@umich.edu system.cpu_voltage_domain) 1033646Srdreslin@umich.edu 1043646Srdreslin@umich.edu# All cpus belong to a common cpu_clk_domain, therefore running at a common 1053646Srdreslin@umich.edu# frequency. 1063646Srdreslin@umich.edufor cpu in system.cpu: 1073646Srdreslin@umich.edu cpu.clk_domain = system.cpu_clk_domain 1083646Srdreslin@umich.edu 1093646Srdreslin@umich.edu# BaseCPU no longer has default values for the BaseCPU.isa 1103646Srdreslin@umich.edu# createThreads() is needed to fill in the cpu.isa 1113646Srdreslin@umich.edufor cpu in system.cpu: 1123646Srdreslin@umich.edu cpu.createThreads() 1133646Srdreslin@umich.edu 1143646Srdreslin@umich.edu# Assign input trace files to the Trace CPU 1153646Srdreslin@umich.edusystem.cpu.instTraceFile=options.inst_trace_file 1163646Srdreslin@umich.edusystem.cpu.dataTraceFile=options.data_trace_file 1173646Srdreslin@umich.edu 1183646Srdreslin@umich.edu# Configure the classic memory system options 1193646Srdreslin@umich.eduMemClass = Simulation.setMemClass(options) 1203646Srdreslin@umich.edusystem.membus = SystemXBar() 1213646Srdreslin@umich.edusystem.system_port = system.membus.slave 1223646Srdreslin@umich.eduCacheConfig.config_cache(options, system) 1233646Srdreslin@umich.eduMemConfig.config_mem(options, system) 1243646Srdreslin@umich.edu 1253646Srdreslin@umich.eduroot = Root(full_system = False, system = system) 1263646Srdreslin@umich.eduSimulation.run(options, root, system, FutureClass) 1273646Srdreslin@umich.edu