etrace_replay.py revision 12564 
1# Copyright (c) 2015 ARM Limited
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35#
36# Authors: Radhika Jagtap
37
38# Basic elastic traces replay script that configures a Trace CPU
39
40from __future__ import print_function
41
42import optparse
43
44from m5.util import addToPath, fatal
45
46addToPath('../')
47
48from common import Options
49from common import Simulation
50from common import CacheConfig
51from common import MemConfig
52from common.Caches import *
53
54parser = optparse.OptionParser()
55Options.addCommonOptions(parser)
56
57if '--ruby' in sys.argv:
58    print("This script does not support Ruby configuration, mainly"
59    " because Trace CPU has been tested only with classic memory system")
60    sys.exit(1)
61
62(options, args) = parser.parse_args()
63
64if args:
65    print("Error: script doesn't take any positional arguments")
66    sys.exit(1)
67
68numThreads = 1
69
70if options.cpu_type != "TraceCPU":
71    fatal("This is a script for elastic trace replay simulation, use "\
72            "--cpu-type=TraceCPU\n");
73
74if options.num_cpus > 1:
75    fatal("This script does not support multi-processor trace replay.\n")
76
77# In this case FutureClass will be None as there is not fast forwarding or
78# switching
79(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
80CPUClass.numThreads = numThreads
81
82system = System(cpu = CPUClass(cpu_id=0),
83                mem_mode = test_mem_mode,
84                mem_ranges = [AddrRange(options.mem_size)],
85                cache_line_size = options.cacheline_size)
86
87# Create a top-level voltage domain
88system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
89
90# Create a source clock for the system. This is used as the clock period for
91# xbar and memory
92system.clk_domain = SrcClockDomain(clock =  options.sys_clock,
93                                   voltage_domain = system.voltage_domain)
94
95# Create a CPU voltage domain
96system.cpu_voltage_domain = VoltageDomain()
97
98# Create a separate clock domain for the CPUs. In case of Trace CPUs this clock
99# is actually used only by the caches connected to the CPU.
100system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
101                                       voltage_domain =
102                                       system.cpu_voltage_domain)
103
104# All cpus belong to a common cpu_clk_domain, therefore running at a common
105# frequency.
106for cpu in system.cpu:
107    cpu.clk_domain = system.cpu_clk_domain
108
109# BaseCPU no longer has default values for the BaseCPU.isa
110# createThreads() is needed to fill in the cpu.isa
111for cpu in system.cpu:
112    cpu.createThreads()
113
114# Assign input trace files to the Trace CPU
115system.cpu.instTraceFile=options.inst_trace_file
116system.cpu.dataTraceFile=options.data_trace_file
117
118# Configure the classic memory system options
119MemClass = Simulation.setMemClass(options)
120system.membus = SystemXBar()
121system.system_port = system.membus.slave
122CacheConfig.config_cache(options, system)
123MemConfig.config_mem(options, system)
124
125root = Root(full_system = False, system = system)
126Simulation.run(options, root, system, FutureClass)
127