devices.py revision 11682
111569Sgabor.dozsa@arm.com# Copyright (c) 2016 ARM Limited 211569Sgabor.dozsa@arm.com# All rights reserved. 311569Sgabor.dozsa@arm.com# 411569Sgabor.dozsa@arm.com# The license below extends only to copyright in the software and shall 511569Sgabor.dozsa@arm.com# not be construed as granting a license to any other intellectual 611569Sgabor.dozsa@arm.com# property including but not limited to intellectual property relating 711569Sgabor.dozsa@arm.com# to a hardware implementation of the functionality of the software 811569Sgabor.dozsa@arm.com# licensed hereunder. You may use the software subject to the license 911569Sgabor.dozsa@arm.com# terms below provided that you ensure that this notice is replicated 1011569Sgabor.dozsa@arm.com# unmodified and in its entirety in all distributions of the software, 1111569Sgabor.dozsa@arm.com# modified or unmodified, in source code or in binary form. 1211569Sgabor.dozsa@arm.com# 1311569Sgabor.dozsa@arm.com# Redistribution and use in source and binary forms, with or without 1411569Sgabor.dozsa@arm.com# modification, are permitted provided that the following conditions are 1511569Sgabor.dozsa@arm.com# met: redistributions of source code must retain the above copyright 1611569Sgabor.dozsa@arm.com# notice, this list of conditions and the following disclaimer; 1711569Sgabor.dozsa@arm.com# redistributions in binary form must reproduce the above copyright 1811569Sgabor.dozsa@arm.com# notice, this list of conditions and the following disclaimer in the 1911569Sgabor.dozsa@arm.com# documentation and/or other materials provided with the distribution; 2011569Sgabor.dozsa@arm.com# neither the name of the copyright holders nor the names of its 2111569Sgabor.dozsa@arm.com# contributors may be used to endorse or promote products derived from 2211569Sgabor.dozsa@arm.com# this software without specific prior written permission. 2311569Sgabor.dozsa@arm.com# 2411569Sgabor.dozsa@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2511569Sgabor.dozsa@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2611569Sgabor.dozsa@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2711569Sgabor.dozsa@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2811569Sgabor.dozsa@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2911569Sgabor.dozsa@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3011569Sgabor.dozsa@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3111569Sgabor.dozsa@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3211569Sgabor.dozsa@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3311569Sgabor.dozsa@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3411569Sgabor.dozsa@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3511569Sgabor.dozsa@arm.com# 3611569Sgabor.dozsa@arm.com# Authors: Andreas Sandberg 3711569Sgabor.dozsa@arm.com# Gabor Dozsa 3811569Sgabor.dozsa@arm.com 3911569Sgabor.dozsa@arm.com# System components used by the bigLITTLE.py configuration script 4011569Sgabor.dozsa@arm.com 4111569Sgabor.dozsa@arm.comimport m5 4211569Sgabor.dozsa@arm.comfrom m5.objects import * 4311682Sandreas.hansson@arm.comm5.util.addToPath('../../') 4411682Sandreas.hansson@arm.comfrom common.Caches import * 4511682Sandreas.hansson@arm.comfrom common import CpuConfig 4611569Sgabor.dozsa@arm.com 4711569Sgabor.dozsa@arm.comclass L1I(L1_ICache): 4811569Sgabor.dozsa@arm.com hit_latency = 1 4911569Sgabor.dozsa@arm.com response_latency = 1 5011569Sgabor.dozsa@arm.com mshrs = 4 5111569Sgabor.dozsa@arm.com tgts_per_mshr = 8 5211569Sgabor.dozsa@arm.com size = '48kB' 5311569Sgabor.dozsa@arm.com assoc = 3 5411569Sgabor.dozsa@arm.com 5511569Sgabor.dozsa@arm.com 5611569Sgabor.dozsa@arm.comclass L1D(L1_DCache): 5711569Sgabor.dozsa@arm.com hit_latency = 2 5811569Sgabor.dozsa@arm.com response_latency = 1 5911569Sgabor.dozsa@arm.com mshrs = 16 6011569Sgabor.dozsa@arm.com tgts_per_mshr = 16 6111569Sgabor.dozsa@arm.com size = '32kB' 6211569Sgabor.dozsa@arm.com assoc = 2 6311569Sgabor.dozsa@arm.com write_buffers = 16 6411569Sgabor.dozsa@arm.com 6511569Sgabor.dozsa@arm.com 6611569Sgabor.dozsa@arm.comclass WalkCache(PageTableWalkerCache): 6711569Sgabor.dozsa@arm.com hit_latency = 4 6811569Sgabor.dozsa@arm.com response_latency = 4 6911569Sgabor.dozsa@arm.com mshrs = 6 7011569Sgabor.dozsa@arm.com tgts_per_mshr = 8 7111569Sgabor.dozsa@arm.com size = '1kB' 7211569Sgabor.dozsa@arm.com assoc = 8 7311569Sgabor.dozsa@arm.com write_buffers = 16 7411569Sgabor.dozsa@arm.com 7511569Sgabor.dozsa@arm.com 7611569Sgabor.dozsa@arm.comclass L2(L2Cache): 7711569Sgabor.dozsa@arm.com hit_latency = 12 7811569Sgabor.dozsa@arm.com response_latency = 5 7911569Sgabor.dozsa@arm.com mshrs = 32 8011569Sgabor.dozsa@arm.com tgts_per_mshr = 8 8111569Sgabor.dozsa@arm.com size = '1MB' 8211569Sgabor.dozsa@arm.com assoc = 16 8311569Sgabor.dozsa@arm.com write_buffers = 8 8411569Sgabor.dozsa@arm.com clusivity='mostly_excl' 8511569Sgabor.dozsa@arm.com 8611569Sgabor.dozsa@arm.com 8711569Sgabor.dozsa@arm.comclass L3(Cache): 8811569Sgabor.dozsa@arm.com size = '16MB' 8911569Sgabor.dozsa@arm.com assoc = 16 9011569Sgabor.dozsa@arm.com hit_latency = 20 9111569Sgabor.dozsa@arm.com response_latency = 20 9211569Sgabor.dozsa@arm.com mshrs = 20 9311569Sgabor.dozsa@arm.com tgts_per_mshr = 12 9411569Sgabor.dozsa@arm.com clusivity='mostly_excl' 9511569Sgabor.dozsa@arm.com 9611569Sgabor.dozsa@arm.com 9711569Sgabor.dozsa@arm.comclass MemBus(SystemXBar): 9811569Sgabor.dozsa@arm.com badaddr_responder = BadAddr(warn_access="warn") 9911569Sgabor.dozsa@arm.com default = Self.badaddr_responder.pio 10011569Sgabor.dozsa@arm.com 10111569Sgabor.dozsa@arm.com 10211630Sgabor.dozsa@arm.comclass CpuCluster(SubSystem): 10311630Sgabor.dozsa@arm.com def __init__(self, system, num_cpus, cpu_clock, cpu_voltage, 10411630Sgabor.dozsa@arm.com cpu_type, l1i_type, l1d_type, wcache_type, l2_type): 10511630Sgabor.dozsa@arm.com super(CpuCluster, self).__init__() 10611630Sgabor.dozsa@arm.com self._cpu_type = cpu_type 10711630Sgabor.dozsa@arm.com self._l1i_type = l1i_type 10811630Sgabor.dozsa@arm.com self._l1d_type = l1d_type 10911630Sgabor.dozsa@arm.com self._wcache_type = wcache_type 11011630Sgabor.dozsa@arm.com self._l2_type = l2_type 11111630Sgabor.dozsa@arm.com 11211630Sgabor.dozsa@arm.com assert num_cpus > 0 11311630Sgabor.dozsa@arm.com 11411630Sgabor.dozsa@arm.com self.voltage_domain = VoltageDomain(voltage=cpu_voltage) 11511630Sgabor.dozsa@arm.com self.clk_domain = SrcClockDomain(clock=cpu_clock, 11611630Sgabor.dozsa@arm.com voltage_domain=self.voltage_domain) 11711630Sgabor.dozsa@arm.com 11811630Sgabor.dozsa@arm.com self.cpus = [ self._cpu_type(cpu_id=system.numCpus() + idx, 11911630Sgabor.dozsa@arm.com clk_domain=self.clk_domain) 12011630Sgabor.dozsa@arm.com for idx in range(num_cpus) ] 12111630Sgabor.dozsa@arm.com 12211630Sgabor.dozsa@arm.com for cpu in self.cpus: 12311630Sgabor.dozsa@arm.com cpu.createThreads() 12411630Sgabor.dozsa@arm.com cpu.createInterruptController() 12511630Sgabor.dozsa@arm.com cpu.socket_id = system.numCpuClusters() 12611630Sgabor.dozsa@arm.com system.addCpuCluster(self, num_cpus) 12711630Sgabor.dozsa@arm.com 12811630Sgabor.dozsa@arm.com def requireCaches(self): 12911630Sgabor.dozsa@arm.com return self._cpu_type.require_caches() 13011630Sgabor.dozsa@arm.com 13111630Sgabor.dozsa@arm.com def memoryMode(self): 13211630Sgabor.dozsa@arm.com return self._cpu_type.memory_mode() 13311630Sgabor.dozsa@arm.com 13411630Sgabor.dozsa@arm.com def addL1(self): 13511630Sgabor.dozsa@arm.com for cpu in self.cpus: 13611630Sgabor.dozsa@arm.com l1i = None if self._l1i_type is None else self._l1i_type() 13711630Sgabor.dozsa@arm.com l1d = None if self._l1d_type is None else self._l1d_type() 13811630Sgabor.dozsa@arm.com iwc = None if self._wcache_type is None else self._wcache_type() 13911630Sgabor.dozsa@arm.com dwc = None if self._wcache_type is None else self._wcache_type() 14011630Sgabor.dozsa@arm.com cpu.addPrivateSplitL1Caches(l1i, l1d, iwc, dwc) 14111630Sgabor.dozsa@arm.com 14211630Sgabor.dozsa@arm.com def addL2(self, clk_domain): 14311630Sgabor.dozsa@arm.com if self._l2_type is None: 14411630Sgabor.dozsa@arm.com return 14511630Sgabor.dozsa@arm.com self.toL2Bus = L2XBar(width=64, clk_domain=clk_domain) 14611630Sgabor.dozsa@arm.com self.l2 = self._l2_type() 14711630Sgabor.dozsa@arm.com for cpu in self.cpus: 14811630Sgabor.dozsa@arm.com cpu.connectAllPorts(self.toL2Bus) 14911630Sgabor.dozsa@arm.com self.toL2Bus.master = self.l2.cpu_side 15011630Sgabor.dozsa@arm.com 15111630Sgabor.dozsa@arm.com def connectMemSide(self, bus): 15211630Sgabor.dozsa@arm.com bus.slave 15311630Sgabor.dozsa@arm.com try: 15411630Sgabor.dozsa@arm.com self.l2.mem_side = bus.slave 15511630Sgabor.dozsa@arm.com except AttributeError: 15611630Sgabor.dozsa@arm.com for cpu in self.cpus: 15711630Sgabor.dozsa@arm.com cpu.connectAllPorts(bus) 15811630Sgabor.dozsa@arm.com 15911630Sgabor.dozsa@arm.com 16011630Sgabor.dozsa@arm.comclass AtomicCluster(CpuCluster): 16111630Sgabor.dozsa@arm.com def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"): 16211630Sgabor.dozsa@arm.com cpu_config = [ CpuConfig.get("atomic"), None, None, None, None ] 16311630Sgabor.dozsa@arm.com super(AtomicCluster, self).__init__(system, num_cpus, cpu_clock, 16411630Sgabor.dozsa@arm.com cpu_voltage, *cpu_config) 16511630Sgabor.dozsa@arm.com def addL1(self): 16611630Sgabor.dozsa@arm.com pass 16711630Sgabor.dozsa@arm.com 16811630Sgabor.dozsa@arm.com 16911569Sgabor.dozsa@arm.comclass SimpleSystem(LinuxArmSystem): 17011569Sgabor.dozsa@arm.com cache_line_size = 64 17111569Sgabor.dozsa@arm.com 17211630Sgabor.dozsa@arm.com def __init__(self, **kwargs): 17311630Sgabor.dozsa@arm.com super(SimpleSystem, self).__init__(**kwargs) 17411569Sgabor.dozsa@arm.com 17511630Sgabor.dozsa@arm.com self.voltage_domain = VoltageDomain(voltage="1.0V") 17611630Sgabor.dozsa@arm.com self.clk_domain = SrcClockDomain(clock="1GHz", 17711630Sgabor.dozsa@arm.com voltage_domain=Parent.voltage_domain) 17811569Sgabor.dozsa@arm.com 17911630Sgabor.dozsa@arm.com self.realview = VExpress_GEM5_V1() 18011569Sgabor.dozsa@arm.com 18111630Sgabor.dozsa@arm.com self.gic_cpu_addr = self.realview.gic.cpu_addr 18211630Sgabor.dozsa@arm.com self.flags_addr = self.realview.realview_io.pio_addr + 0x30 18311569Sgabor.dozsa@arm.com 18411630Sgabor.dozsa@arm.com self.membus = MemBus() 18511569Sgabor.dozsa@arm.com 18611630Sgabor.dozsa@arm.com self.intrctrl = IntrControl() 18711630Sgabor.dozsa@arm.com self.terminal = Terminal() 18811630Sgabor.dozsa@arm.com self.vncserver = VncServer() 18911569Sgabor.dozsa@arm.com 19011630Sgabor.dozsa@arm.com self.iobus = IOXBar() 19111630Sgabor.dozsa@arm.com # CPUs->PIO 19211630Sgabor.dozsa@arm.com self.iobridge = Bridge(delay='50ns') 19311630Sgabor.dozsa@arm.com # Device DMA -> MEM 19411630Sgabor.dozsa@arm.com self.dmabridge = Bridge(delay='50ns', 19511630Sgabor.dozsa@arm.com ranges=self.realview._mem_regions) 19611630Sgabor.dozsa@arm.com 19711630Sgabor.dozsa@arm.com self._pci_devices = 0 19811630Sgabor.dozsa@arm.com self._clusters = [] 19911630Sgabor.dozsa@arm.com self._num_cpus = 0 20011569Sgabor.dozsa@arm.com 20111569Sgabor.dozsa@arm.com def attach_pci(self, dev): 20211569Sgabor.dozsa@arm.com dev.pci_bus, dev.pci_dev, dev.pci_func = (0, self._pci_devices + 1, 0) 20311569Sgabor.dozsa@arm.com self._pci_devices += 1 20411569Sgabor.dozsa@arm.com self.realview.attachPciDevice(dev, self.iobus) 20511569Sgabor.dozsa@arm.com 20611569Sgabor.dozsa@arm.com def connect(self): 20711569Sgabor.dozsa@arm.com self.iobridge.master = self.iobus.slave 20811569Sgabor.dozsa@arm.com self.iobridge.slave = self.membus.master 20911569Sgabor.dozsa@arm.com 21011569Sgabor.dozsa@arm.com self.dmabridge.master = self.membus.slave 21111569Sgabor.dozsa@arm.com self.dmabridge.slave = self.iobus.master 21211569Sgabor.dozsa@arm.com 21311569Sgabor.dozsa@arm.com self.gic_cpu_addr = self.realview.gic.cpu_addr 21411569Sgabor.dozsa@arm.com self.realview.attachOnChipIO(self.membus, self.iobridge) 21511569Sgabor.dozsa@arm.com self.realview.attachIO(self.iobus) 21611569Sgabor.dozsa@arm.com self.system_port = self.membus.slave 21711630Sgabor.dozsa@arm.com 21811630Sgabor.dozsa@arm.com def numCpuClusters(self): 21911630Sgabor.dozsa@arm.com return len(self._clusters) 22011630Sgabor.dozsa@arm.com 22111630Sgabor.dozsa@arm.com def addCpuCluster(self, cpu_cluster, num_cpus): 22211630Sgabor.dozsa@arm.com assert cpu_cluster not in self._clusters 22311630Sgabor.dozsa@arm.com assert num_cpus > 0 22411630Sgabor.dozsa@arm.com self._clusters.append(cpu_cluster) 22511630Sgabor.dozsa@arm.com self._num_cpus += num_cpus 22611630Sgabor.dozsa@arm.com 22711630Sgabor.dozsa@arm.com def numCpus(self): 22811630Sgabor.dozsa@arm.com return self._num_cpus 22911630Sgabor.dozsa@arm.com 23011630Sgabor.dozsa@arm.com def addCaches(self, need_caches, last_cache_level): 23111630Sgabor.dozsa@arm.com if not need_caches: 23211630Sgabor.dozsa@arm.com # connect each cluster to the memory hierarchy 23311630Sgabor.dozsa@arm.com for cluster in self._clusters: 23411630Sgabor.dozsa@arm.com cluster.connectMemSide(self.membus) 23511630Sgabor.dozsa@arm.com return 23611630Sgabor.dozsa@arm.com 23711630Sgabor.dozsa@arm.com cluster_mem_bus = self.membus 23811630Sgabor.dozsa@arm.com assert last_cache_level >= 1 and last_cache_level <= 3 23911630Sgabor.dozsa@arm.com for cluster in self._clusters: 24011630Sgabor.dozsa@arm.com cluster.addL1() 24111630Sgabor.dozsa@arm.com if last_cache_level > 1: 24211630Sgabor.dozsa@arm.com for cluster in self._clusters: 24311630Sgabor.dozsa@arm.com cluster.addL2(cluster.clk_domain) 24411630Sgabor.dozsa@arm.com if last_cache_level > 2: 24511630Sgabor.dozsa@arm.com max_clock_cluster = max(self._clusters, 24611630Sgabor.dozsa@arm.com key=lambda c: c.clk_domain.clock[0]) 24711630Sgabor.dozsa@arm.com self.l3 = L3(clk_domain=max_clock_cluster.clk_domain) 24811630Sgabor.dozsa@arm.com self.toL3Bus = L2XBar(width=64) 24911630Sgabor.dozsa@arm.com self.toL3Bus.master = self.l3.cpu_side 25011630Sgabor.dozsa@arm.com self.l3.mem_side = self.membus.slave 25111630Sgabor.dozsa@arm.com cluster_mem_bus = self.toL3Bus 25211630Sgabor.dozsa@arm.com 25311630Sgabor.dozsa@arm.com # connect each cluster to the memory hierarchy 25411630Sgabor.dozsa@arm.com for cluster in self._clusters: 25511630Sgabor.dozsa@arm.com cluster.connectMemSide(cluster_mem_bus) 256