sweep.py revision 10219
110139Sandreas.hansson@arm.com# Copyright (c) 2014 ARM Limited 210139Sandreas.hansson@arm.com# All rights reserved. 310139Sandreas.hansson@arm.com# 410139Sandreas.hansson@arm.com# The license below extends only to copyright in the software and shall 510139Sandreas.hansson@arm.com# not be construed as granting a license to any other intellectual 610139Sandreas.hansson@arm.com# property including but not limited to intellectual property relating 710139Sandreas.hansson@arm.com# to a hardware implementation of the functionality of the software 810139Sandreas.hansson@arm.com# licensed hereunder. You may use the software subject to the license 910139Sandreas.hansson@arm.com# terms below provided that you ensure that this notice is replicated 1010139Sandreas.hansson@arm.com# unmodified and in its entirety in all distributions of the software, 1110139Sandreas.hansson@arm.com# modified or unmodified, in source code or in binary form. 1210139Sandreas.hansson@arm.com# 1310139Sandreas.hansson@arm.com# Redistribution and use in source and binary forms, with or without 1410139Sandreas.hansson@arm.com# modification, are permitted provided that the following conditions are 1510139Sandreas.hansson@arm.com# met: redistributions of source code must retain the above copyright 1610139Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer; 1710139Sandreas.hansson@arm.com# redistributions in binary form must reproduce the above copyright 1810139Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer in the 1910139Sandreas.hansson@arm.com# documentation and/or other materials provided with the distribution; 2010139Sandreas.hansson@arm.com# neither the name of the copyright holders nor the names of its 2110139Sandreas.hansson@arm.com# contributors may be used to endorse or promote products derived from 2210139Sandreas.hansson@arm.com# this software without specific prior written permission. 2310139Sandreas.hansson@arm.com# 2410139Sandreas.hansson@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2510139Sandreas.hansson@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2610139Sandreas.hansson@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2710139Sandreas.hansson@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2810139Sandreas.hansson@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2910139Sandreas.hansson@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3010139Sandreas.hansson@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3110139Sandreas.hansson@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3210139Sandreas.hansson@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3310139Sandreas.hansson@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3410139Sandreas.hansson@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3510139Sandreas.hansson@arm.com# 3610139Sandreas.hansson@arm.com# Authors: Andreas Hansson 3710139Sandreas.hansson@arm.com 3810139Sandreas.hansson@arm.comimport optparse 3910139Sandreas.hansson@arm.com 4010139Sandreas.hansson@arm.comimport m5 4110139Sandreas.hansson@arm.comfrom m5.objects import * 4210139Sandreas.hansson@arm.comfrom m5.util import addToPath 4310139Sandreas.hansson@arm.comfrom m5.internal.stats import periodicStatDump 4410139Sandreas.hansson@arm.com 4510139Sandreas.hansson@arm.comaddToPath('../common') 4610139Sandreas.hansson@arm.com 4710139Sandreas.hansson@arm.comimport MemConfig 4810139Sandreas.hansson@arm.com 4910139Sandreas.hansson@arm.com# this script is helpful to sweep the efficiency of a specific memory 5010139Sandreas.hansson@arm.com# controller configuration, by varying the number of banks accessed, 5110139Sandreas.hansson@arm.com# and the sequential stride size (how many bytes per activate), and 5210139Sandreas.hansson@arm.com# observe what bus utilisation (bandwidth) is achieved 5310139Sandreas.hansson@arm.com 5410139Sandreas.hansson@arm.comparser = optparse.OptionParser() 5510139Sandreas.hansson@arm.com 5610139Sandreas.hansson@arm.com# Use a single-channel DDR3-1600 x64 by default 5710139Sandreas.hansson@arm.comparser.add_option("--mem-type", type="choice", default="ddr3_1600_x64", 5810139Sandreas.hansson@arm.com choices=MemConfig.mem_names(), 5910139Sandreas.hansson@arm.com help = "type of memory to use") 6010139Sandreas.hansson@arm.com 6110139Sandreas.hansson@arm.com(options, args) = parser.parse_args() 6210139Sandreas.hansson@arm.com 6310139Sandreas.hansson@arm.comif args: 6410139Sandreas.hansson@arm.com print "Error: script doesn't take any positional arguments" 6510139Sandreas.hansson@arm.com sys.exit(1) 6610139Sandreas.hansson@arm.com 6710139Sandreas.hansson@arm.com# at the moment we stay with the default open-adaptive page policy, 6810139Sandreas.hansson@arm.com# and address mapping 6910139Sandreas.hansson@arm.com 7010219Sandreas.hansson@arm.com# start with the system itself, using a multi-layer 1.5 GHz 7110139Sandreas.hansson@arm.com# bus/crossbar, delivering 64 bytes / 5 cycles (one header cycle) 7210219Sandreas.hansson@arm.com# which amounts to 19.2 GByte/s per layer and thus per port 7310139Sandreas.hansson@arm.comsystem = System(membus = NoncoherentBus(width = 16)) 7410219Sandreas.hansson@arm.comsystem.clk_domain = SrcClockDomain(clock = '1.5GHz', 7510139Sandreas.hansson@arm.com voltage_domain = 7610139Sandreas.hansson@arm.com VoltageDomain(voltage = '1V')) 7710139Sandreas.hansson@arm.com 7810139Sandreas.hansson@arm.com# we are fine with 256 MB memory for now 7910139Sandreas.hansson@arm.commem_range = AddrRange('256MB') 8010139Sandreas.hansson@arm.comsystem.mem_ranges = [mem_range] 8110139Sandreas.hansson@arm.com 8210139Sandreas.hansson@arm.com# force a single channel to match the assumptions in the DRAM traffic 8310139Sandreas.hansson@arm.com# generator 8410139Sandreas.hansson@arm.comoptions.mem_channels = 1 8510139Sandreas.hansson@arm.comMemConfig.config_mem(options, system) 8610139Sandreas.hansson@arm.com 8710139Sandreas.hansson@arm.com# the following assumes that we are using the native DRAM 8810139Sandreas.hansson@arm.com# controller, check to be sure 8910146Sandreas.hansson@arm.comif not isinstance(system.mem_ctrls[0], m5.objects.DRAMCtrl): 9010146Sandreas.hansson@arm.com fatal("This script assumes the memory is a DRAMCtrl subclass") 9110139Sandreas.hansson@arm.com 9210139Sandreas.hansson@arm.com# for now the generator assumes a single rank 9310139Sandreas.hansson@arm.comsystem.mem_ctrls[0].ranks_per_channel = 1 9410139Sandreas.hansson@arm.com 9510139Sandreas.hansson@arm.com# stay in each state for 0.25 ms, long enough to warm things up, and 9610139Sandreas.hansson@arm.com# short enough to avoid hitting a refresh 9710139Sandreas.hansson@arm.comperiod = 250000000 9810139Sandreas.hansson@arm.com 9910139Sandreas.hansson@arm.com# this is where we go off piste, and print the traffic generator 10010139Sandreas.hansson@arm.com# configuration that we will later use, crazy but it works 10110139Sandreas.hansson@arm.comcfg_file_name = "configs/dram/sweep.cfg" 10210139Sandreas.hansson@arm.comcfg_file = open(cfg_file_name, 'w') 10310139Sandreas.hansson@arm.com 10410139Sandreas.hansson@arm.com# stay in each state as long as the dump/reset period, use the entire 10510139Sandreas.hansson@arm.com# range, issue transactions of the right DRAM burst size, and match 10610139Sandreas.hansson@arm.com# the DRAM maximum bandwidth to ensure that it is saturated 10710139Sandreas.hansson@arm.com 10810139Sandreas.hansson@arm.com# get the number of banks 10910139Sandreas.hansson@arm.comnbr_banks = system.mem_ctrls[0].banks_per_rank.value 11010139Sandreas.hansson@arm.com 11110139Sandreas.hansson@arm.com# determine the burst length in bytes 11210139Sandreas.hansson@arm.comburst_size = int((system.mem_ctrls[0].devices_per_rank.value * 11310139Sandreas.hansson@arm.com system.mem_ctrls[0].device_bus_width.value * 11410139Sandreas.hansson@arm.com system.mem_ctrls[0].burst_length.value) / 8) 11510139Sandreas.hansson@arm.com 11610139Sandreas.hansson@arm.com# next, get the page size in bytes 11710139Sandreas.hansson@arm.compage_size = system.mem_ctrls[0].devices_per_rank.value * \ 11810139Sandreas.hansson@arm.com system.mem_ctrls[0].device_rowbuffer_size.value 11910139Sandreas.hansson@arm.com 12010139Sandreas.hansson@arm.com# match the maximum bandwidth of the memory, the parameter is in ns 12110139Sandreas.hansson@arm.com# and we need it in ticks 12210139Sandreas.hansson@arm.comitt = system.mem_ctrls[0].tBURST.value * 1000000000000 12310139Sandreas.hansson@arm.com 12410139Sandreas.hansson@arm.com# assume we start at 0 12510139Sandreas.hansson@arm.commax_addr = mem_range.end 12610139Sandreas.hansson@arm.com 12710139Sandreas.hansson@arm.com# now we create the state by iterating over the stride size from burst 12810139Sandreas.hansson@arm.com# size to min of the page size and 1 kB, and from using only a single 12910139Sandreas.hansson@arm.com# bank up to the number of banks available 13010139Sandreas.hansson@arm.comnxt_state = 0 13110139Sandreas.hansson@arm.comfor bank in range(1, nbr_banks + 1): 13210139Sandreas.hansson@arm.com for stride_size in range(burst_size, min(1024, page_size) + 1, burst_size): 13310139Sandreas.hansson@arm.com cfg_file.write("STATE %d %d DRAM 100 0 %d " 13410139Sandreas.hansson@arm.com "%d %d %d %d %d %d %d %d 1\n" % 13510139Sandreas.hansson@arm.com (nxt_state, period, max_addr, burst_size, itt, itt, 0, 13610139Sandreas.hansson@arm.com stride_size, page_size, nbr_banks, bank)) 13710139Sandreas.hansson@arm.com nxt_state = nxt_state + 1 13810139Sandreas.hansson@arm.com 13910139Sandreas.hansson@arm.comcfg_file.write("INIT 0\n") 14010139Sandreas.hansson@arm.com 14110139Sandreas.hansson@arm.com# go through the states one by one 14210139Sandreas.hansson@arm.comfor state in range(1, nxt_state): 14310139Sandreas.hansson@arm.com cfg_file.write("TRANSITION %d %d 1\n" % (state - 1, state)) 14410139Sandreas.hansson@arm.com 14510139Sandreas.hansson@arm.comcfg_file.write("TRANSITION %d %d 1\n" % (nxt_state - 1, nxt_state - 1)) 14610139Sandreas.hansson@arm.com 14710139Sandreas.hansson@arm.comcfg_file.close() 14810139Sandreas.hansson@arm.com 14910139Sandreas.hansson@arm.com# create a traffic generator, and point it to the file we just created 15010139Sandreas.hansson@arm.comsystem.tgen = TrafficGen(config_file = cfg_file_name) 15110139Sandreas.hansson@arm.com 15210139Sandreas.hansson@arm.com# add a communication monitor 15310139Sandreas.hansson@arm.comsystem.monitor = CommMonitor() 15410139Sandreas.hansson@arm.com 15510139Sandreas.hansson@arm.com# connect the traffic generator to the bus via a communication monitor 15610139Sandreas.hansson@arm.comsystem.tgen.port = system.monitor.slave 15710139Sandreas.hansson@arm.comsystem.monitor.master = system.membus.slave 15810139Sandreas.hansson@arm.com 15910139Sandreas.hansson@arm.com# connect the system port even if it is not used in this example 16010139Sandreas.hansson@arm.comsystem.system_port = system.membus.slave 16110139Sandreas.hansson@arm.com 16210139Sandreas.hansson@arm.com# every period, dump and reset all stats 16310139Sandreas.hansson@arm.comperiodicStatDump(period) 16410139Sandreas.hansson@arm.com 16510139Sandreas.hansson@arm.com# run Forrest, run! 16610139Sandreas.hansson@arm.comroot = Root(full_system = False, system = system) 16710139Sandreas.hansson@arm.comroot.system.mem_mode = 'timing' 16810139Sandreas.hansson@arm.com 16910139Sandreas.hansson@arm.comm5.instantiate() 17010139Sandreas.hansson@arm.comm5.simulate(nxt_state * period) 171