sweep.py revision 10219
1# Copyright (c) 2014 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Redistribution and use in source and binary forms, with or without 14# modification, are permitted provided that the following conditions are 15# met: redistributions of source code must retain the above copyright 16# notice, this list of conditions and the following disclaimer; 17# redistributions in binary form must reproduce the above copyright 18# notice, this list of conditions and the following disclaimer in the 19# documentation and/or other materials provided with the distribution; 20# neither the name of the copyright holders nor the names of its 21# contributors may be used to endorse or promote products derived from 22# this software without specific prior written permission. 23# 24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# 36# Authors: Andreas Hansson 37 38import optparse 39 40import m5 41from m5.objects import * 42from m5.util import addToPath 43from m5.internal.stats import periodicStatDump 44 45addToPath('../common') 46 47import MemConfig 48 49# this script is helpful to sweep the efficiency of a specific memory 50# controller configuration, by varying the number of banks accessed, 51# and the sequential stride size (how many bytes per activate), and 52# observe what bus utilisation (bandwidth) is achieved 53 54parser = optparse.OptionParser() 55 56# Use a single-channel DDR3-1600 x64 by default 57parser.add_option("--mem-type", type="choice", default="ddr3_1600_x64", 58 choices=MemConfig.mem_names(), 59 help = "type of memory to use") 60 61(options, args) = parser.parse_args() 62 63if args: 64 print "Error: script doesn't take any positional arguments" 65 sys.exit(1) 66 67# at the moment we stay with the default open-adaptive page policy, 68# and address mapping 69 70# start with the system itself, using a multi-layer 1.5 GHz 71# bus/crossbar, delivering 64 bytes / 5 cycles (one header cycle) 72# which amounts to 19.2 GByte/s per layer and thus per port 73system = System(membus = NoncoherentBus(width = 16)) 74system.clk_domain = SrcClockDomain(clock = '1.5GHz', 75 voltage_domain = 76 VoltageDomain(voltage = '1V')) 77 78# we are fine with 256 MB memory for now 79mem_range = AddrRange('256MB') 80system.mem_ranges = [mem_range] 81 82# force a single channel to match the assumptions in the DRAM traffic 83# generator 84options.mem_channels = 1 85MemConfig.config_mem(options, system) 86 87# the following assumes that we are using the native DRAM 88# controller, check to be sure 89if not isinstance(system.mem_ctrls[0], m5.objects.DRAMCtrl): 90 fatal("This script assumes the memory is a DRAMCtrl subclass") 91 92# for now the generator assumes a single rank 93system.mem_ctrls[0].ranks_per_channel = 1 94 95# stay in each state for 0.25 ms, long enough to warm things up, and 96# short enough to avoid hitting a refresh 97period = 250000000 98 99# this is where we go off piste, and print the traffic generator 100# configuration that we will later use, crazy but it works 101cfg_file_name = "configs/dram/sweep.cfg" 102cfg_file = open(cfg_file_name, 'w') 103 104# stay in each state as long as the dump/reset period, use the entire 105# range, issue transactions of the right DRAM burst size, and match 106# the DRAM maximum bandwidth to ensure that it is saturated 107 108# get the number of banks 109nbr_banks = system.mem_ctrls[0].banks_per_rank.value 110 111# determine the burst length in bytes 112burst_size = int((system.mem_ctrls[0].devices_per_rank.value * 113 system.mem_ctrls[0].device_bus_width.value * 114 system.mem_ctrls[0].burst_length.value) / 8) 115 116# next, get the page size in bytes 117page_size = system.mem_ctrls[0].devices_per_rank.value * \ 118 system.mem_ctrls[0].device_rowbuffer_size.value 119 120# match the maximum bandwidth of the memory, the parameter is in ns 121# and we need it in ticks 122itt = system.mem_ctrls[0].tBURST.value * 1000000000000 123 124# assume we start at 0 125max_addr = mem_range.end 126 127# now we create the state by iterating over the stride size from burst 128# size to min of the page size and 1 kB, and from using only a single 129# bank up to the number of banks available 130nxt_state = 0 131for bank in range(1, nbr_banks + 1): 132 for stride_size in range(burst_size, min(1024, page_size) + 1, burst_size): 133 cfg_file.write("STATE %d %d DRAM 100 0 %d " 134 "%d %d %d %d %d %d %d %d 1\n" % 135 (nxt_state, period, max_addr, burst_size, itt, itt, 0, 136 stride_size, page_size, nbr_banks, bank)) 137 nxt_state = nxt_state + 1 138 139cfg_file.write("INIT 0\n") 140 141# go through the states one by one 142for state in range(1, nxt_state): 143 cfg_file.write("TRANSITION %d %d 1\n" % (state - 1, state)) 144 145cfg_file.write("TRANSITION %d %d 1\n" % (nxt_state - 1, nxt_state - 1)) 146 147cfg_file.close() 148 149# create a traffic generator, and point it to the file we just created 150system.tgen = TrafficGen(config_file = cfg_file_name) 151 152# add a communication monitor 153system.monitor = CommMonitor() 154 155# connect the traffic generator to the bus via a communication monitor 156system.tgen.port = system.monitor.slave 157system.monitor.master = system.membus.slave 158 159# connect the system port even if it is not used in this example 160system.system_port = system.membus.slave 161 162# every period, dump and reset all stats 163periodicStatDump(period) 164 165# run Forrest, run! 166root = Root(full_system = False, system = system) 167root.system.mem_mode = 'timing' 168 169m5.instantiate() 170m5.simulate(nxt_state * period) 171