ex5_big.py revision 12097
1# Copyright (c) 2012 The Regents of The University of Michigan 2# Copyright (c) 2016 Centre National de la Recherche Scientifique 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; 9# redistributions in binary form must reproduce the above copyright 10# notice, this list of conditions and the following disclaimer in the 11# documentation and/or other materials provided with the distribution; 12# neither the name of the copyright holders nor the names of its 13# contributors may be used to endorse or promote products derived from 14# this software without specific prior written permission. 15# 16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27# 28# Authors: Ron Dreslinski 29# Anastasiia Butko 30# Louisa Bessad 31 32from m5.objects import * 33 34#----------------------------------------------------------------------- 35# ex5 big core (based on the ARM Cortex-A15) 36#----------------------------------------------------------------------- 37 38# Simple ALU Instructions have a latency of 1 39class ex5_big_Simple_Int(FUDesc): 40 opList = [ OpDesc(opClass='IntAlu', opLat=1) ] 41 count = 2 42 43# Complex ALU instructions have a variable latencies 44class ex5_big_Complex_Int(FUDesc): 45 opList = [ OpDesc(opClass='IntMult', opLat=4, pipelined=True), 46 OpDesc(opClass='IntDiv', opLat=11, pipelined=False), 47 OpDesc(opClass='IprAccess', opLat=3, pipelined=True) ] 48 count = 1 49 50# Floating point and SIMD instructions 51class ex5_big_FP(FUDesc): 52 opList = [ OpDesc(opClass='SimdAdd', opLat=3), 53 OpDesc(opClass='SimdAddAcc', opLat=4), 54 OpDesc(opClass='SimdAlu', opLat=4), 55 OpDesc(opClass='SimdCmp', opLat=4), 56 OpDesc(opClass='SimdCvt', opLat=3), 57 OpDesc(opClass='SimdMisc', opLat=3), 58 OpDesc(opClass='SimdMult',opLat=6), 59 OpDesc(opClass='SimdMultAcc',opLat=5), 60 OpDesc(opClass='SimdShift',opLat=3), 61 OpDesc(opClass='SimdShiftAcc', opLat=3), 62 OpDesc(opClass='SimdSqrt', opLat=9), 63 OpDesc(opClass='SimdFloatAdd',opLat=6), 64 OpDesc(opClass='SimdFloatAlu',opLat=5), 65 OpDesc(opClass='SimdFloatCmp', opLat=3), 66 OpDesc(opClass='SimdFloatCvt', opLat=3), 67 OpDesc(opClass='SimdFloatDiv', opLat=21), 68 OpDesc(opClass='SimdFloatMisc', opLat=3), 69 OpDesc(opClass='SimdFloatMult', opLat=6), 70 OpDesc(opClass='SimdFloatMultAcc',opLat=1), 71 OpDesc(opClass='SimdFloatSqrt', opLat=9), 72 OpDesc(opClass='FloatAdd', opLat=6), 73 OpDesc(opClass='FloatCmp', opLat=5), 74 OpDesc(opClass='FloatCvt', opLat=5), 75 OpDesc(opClass='FloatDiv', opLat=12, pipelined=False), 76 OpDesc(opClass='FloatSqrt', opLat=33, pipelined=False), 77 OpDesc(opClass='FloatMult', opLat=8) ] 78 count = 2 79 80 81# Load/Store Units 82class ex5_big_Load(FUDesc): 83 opList = [ OpDesc(opClass='MemRead',opLat=2) ] 84 count = 1 85 86class ex5_big_Store(FUDesc): 87 opList = [OpDesc(opClass='MemWrite',opLat=2) ] 88 count = 1 89 90# Functional Units for this CPU 91class ex5_big_FUP(FUPool): 92 FUList = [ex5_big_Simple_Int(), ex5_big_Complex_Int(), 93 ex5_big_Load(), ex5_big_Store(), ex5_big_FP()] 94 95# Bi-Mode Branch Predictor 96class ex5_big_BP(BiModeBP): 97 globalPredictorSize = 4096 98 globalCtrBits = 2 99 choicePredictorSize = 1024 100 choiceCtrBits = 3 101 BTBEntries = 4096 102 BTBTagSize = 18 103 RASSize = 48 104 instShiftAmt = 2 105 106class ex5_big(DerivO3CPU): 107 LQEntries = 16 108 SQEntries = 16 109 LSQDepCheckShift = 0 110 LFSTSize = 1024 111 SSITSize = 1024 112 decodeToFetchDelay = 1 113 renameToFetchDelay = 1 114 iewToFetchDelay = 1 115 commitToFetchDelay = 1 116 renameToDecodeDelay = 1 117 iewToDecodeDelay = 1 118 commitToDecodeDelay = 1 119 iewToRenameDelay = 1 120 commitToRenameDelay = 1 121 commitToIEWDelay = 1 122 fetchWidth = 3 123 fetchBufferSize = 16 124 fetchToDecodeDelay = 3 125 decodeWidth = 3 126 decodeToRenameDelay = 2 127 renameWidth = 3 128 renameToIEWDelay = 1 129 issueToExecuteDelay = 1 130 dispatchWidth = 6 131 issueWidth = 8 132 wbWidth = 8 133 fuPool = ex5_big_FUP() 134 iewToCommitDelay = 1 135 renameToROBDelay = 1 136 commitWidth = 8 137 squashWidth = 8 138 trapLatency = 13 139 backComSize = 5 140 forwardComSize = 5 141 numPhysIntRegs = 90 142 numPhysFloatRegs = 256 143 numIQEntries = 48 144 numROBEntries = 60 145 146 switched_out = False 147 branchPred = ex5_big_BP() 148 149class L1Cache(Cache): 150 tag_latency = 2 151 data_latency = 2 152 response_latency = 2 153 tgts_per_mshr = 8 154 # Consider the L2 a victim cache also for clean lines 155 writeback_clean = True 156 157# Instruction Cache 158class L1I(L1Cache): 159 mshrs = 2 160 size = '32kB' 161 assoc = 2 162 is_read_only = True 163 164# Data Cache 165class L1D(L1Cache): 166 mshrs = 6 167 size = '32kB' 168 assoc = 2 169 write_buffers = 16 170 171# TLB Cache 172# Use a cache as a L2 TLB 173class WalkCache(Cache): 174 tag_latency = 4 175 data_latency = 4 176 response_latency = 4 177 mshrs = 6 178 tgts_per_mshr = 8 179 size = '1kB' 180 assoc = 8 181 write_buffers = 16 182 is_read_only = True 183 # Writeback clean lines as well 184 writeback_clean = True 185 186# L2 Cache 187class L2(Cache): 188 tag_latency = 15 189 data_latency = 15 190 response_latency = 15 191 mshrs = 16 192 tgts_per_mshr = 8 193 size = '2MB' 194 assoc = 16 195 write_buffers = 8 196 prefetch_on_access = True 197 clusivity = 'mostly_excl' 198 # Simple stride prefetcher 199 prefetcher = StridePrefetcher(degree=8, latency = 1) 200 tags = RandomRepl() 201